From patchwork Thu Mar 23 16:38:32 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Iremonger, Bernard" X-Patchwork-Id: 22188 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [IPv6:::1]) by dpdk.org (Postfix) with ESMTP id F354969C5; Thu, 23 Mar 2017 17:39:06 +0100 (CET) Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by dpdk.org (Postfix) with ESMTP id 86D8011C5 for ; Thu, 23 Mar 2017 17:38:47 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=intel.com; i=@intel.com; q=dns/txt; s=intel; t=1490287127; x=1521823127; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=31TBZo8MJzmGWGObzDFso6+mezVBM6yNDZzQrH8sg18=; b=eaB3ngZxAJtpBAlOdOlTZIJZArgIZdw1cBjhPIhC6CrI2unb1rZTvN/E OfE8VC5LFpxaKdyVody/JR50kJn4uw==; Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga103.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 23 Mar 2017 09:38:47 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos; i="5.36,210,1486454400"; d="scan'208"; a="1126276480" Received: from sivswdev01.ir.intel.com (HELO localhost.localdomain) ([10.237.217.45]) by fmsmga001.fm.intel.com with ESMTP; 23 Mar 2017 09:38:45 -0700 From: Bernard Iremonger To: dev@dpdk.org, beilei.xing@intel.com, jingjing.wu@intel.com Cc: helin.zhang@intel.com, Bernard Iremonger Date: Thu, 23 Mar 2017 16:38:32 +0000 Message-Id: <1490287113-8895-3-git-send-email-bernard.iremonger@intel.com> X-Mailer: git-send-email 1.7.0.7 In-Reply-To: <1488552491-20432-1-git-send-email-bernard.iremonger@intel.com> References: <1488552491-20432-1-git-send-email-bernard.iremonger@intel.com> Subject: [dpdk-dev] [PATCH v2 2/3] net/i40e: parse QinQ pattern X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" add QinQ pattern. add i40e_flow_parse_qinq_pattern function. add i40e_flow_parse_qinq_filter function. Signed-off-by: Bernard Iremonger --- drivers/net/i40e/i40e_flow.c | 194 ++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 192 insertions(+), 2 deletions(-) diff --git a/drivers/net/i40e/i40e_flow.c b/drivers/net/i40e/i40e_flow.c index 8d7765a..e53ab22 100644 --- a/drivers/net/i40e/i40e_flow.c +++ b/drivers/net/i40e/i40e_flow.c @@ -1,7 +1,7 @@ /*- * BSD LICENSE * - * Copyright (c) 2016 Intel Corporation. All rights reserved. + * Copyright (c) 2016-2017 Intel Corporation. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -128,6 +128,18 @@ static int i40e_flow_destroy_tunnel_filter(struct i40e_pf *pf, static int i40e_flow_flush_fdir_filter(struct i40e_pf *pf); static int i40e_flow_flush_ethertype_filter(struct i40e_pf *pf); static int i40e_flow_flush_tunnel_filter(struct i40e_pf *pf); +static int +i40e_flow_parse_qinq_filter(struct rte_eth_dev *dev, + const struct rte_flow_attr *attr, + const struct rte_flow_item pattern[], + const struct rte_flow_action actions[], + struct rte_flow_error *error, + union i40e_filter_t *filter); +static int +i40e_flow_parse_qinq_pattern(__rte_unused struct rte_eth_dev *dev, + const struct rte_flow_item *pattern, + struct rte_flow_error *error, + struct i40e_tunnel_filter_conf *filter); const struct rte_flow_ops i40e_flow_ops = { .validate = i40e_flow_validate, @@ -318,6 +330,14 @@ static enum rte_flow_item_type pattern_mpls_4[] = { RTE_FLOW_ITEM_TYPE_END, }; +/* Pattern matched QINQ */ +static enum rte_flow_item_type pattern_qinq_1[] = { + RTE_FLOW_ITEM_TYPE_ETH, + RTE_FLOW_ITEM_TYPE_VLAN, + RTE_FLOW_ITEM_TYPE_VLAN, + RTE_FLOW_ITEM_TYPE_END, +}; + static struct i40e_valid_pattern i40e_supported_patterns[] = { /* Ethertype */ { pattern_ethertype, i40e_flow_parse_ethertype_filter }, @@ -348,6 +368,8 @@ static struct i40e_valid_pattern i40e_supported_patterns[] = { { pattern_mpls_2, i40e_flow_parse_mpls_filter }, { pattern_mpls_3, i40e_flow_parse_mpls_filter }, { pattern_mpls_4, i40e_flow_parse_mpls_filter }, + /* QINQ */ + { pattern_qinq_1, i40e_flow_parse_qinq_filter }, }; #define NEXT_ITEM_OF_ACTION(act, actions, index) \ @@ -1171,7 +1193,7 @@ i40e_flow_parse_fdir_filter(struct rte_eth_dev *dev, return 0; } -/* Parse to get the action info of a tunnle filter +/* Parse to get the action info of a tunnel filter * Tunnel action only supports PF, VF and QUEUE. */ static int @@ -1721,6 +1743,174 @@ i40e_flow_parse_mpls_filter(struct rte_eth_dev *dev, } static int +i40e_flow_parse_qinq_pattern(__rte_unused struct rte_eth_dev *dev, + const struct rte_flow_item *pattern, + struct rte_flow_error *error, + struct i40e_tunnel_filter_conf *filter) +{ + const struct rte_flow_item *item = pattern; + const struct rte_flow_item_eth *eth_spec; + const struct rte_flow_item_eth *eth_mask; + const struct rte_flow_item_eth *i_eth_spec = NULL; + const struct rte_flow_item_eth *i_eth_mask = NULL; + const struct rte_flow_item_vlan *vlan_spec = NULL; + const struct rte_flow_item_vlan *vlan_mask = NULL; + const struct rte_flow_item_vlan *i_vlan_spec = NULL; + const struct rte_flow_item_vlan *o_vlan_spec = NULL; + + enum rte_flow_item_type item_type; + bool vlan_flag = 0; + + for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) { + if (item->last) { + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ITEM, + item, + "Not support range"); + return -rte_errno; + } + item_type = item->type; + switch (item_type) { + case RTE_FLOW_ITEM_TYPE_ETH: + eth_spec = (const struct rte_flow_item_eth *)item->spec; + eth_mask = (const struct rte_flow_item_eth *)item->mask; + if ((!eth_spec && eth_mask) || + (eth_spec && !eth_mask)) { + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ITEM, + item, + "Invalid ether spec/mask"); + return -rte_errno; + } + + if (eth_spec && eth_mask) { + /* DST address of inner MAC shouldn't be masked. + * SRC address of Inner MAC should be masked. + */ + if (!is_broadcast_ether_addr(ð_mask->dst) || + !is_zero_ether_addr(ð_mask->src) || + eth_mask->type) { + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ITEM, + item, + "Invalid ether spec/mask"); + return -rte_errno; + } + + rte_memcpy(&filter->outer_mac, + ð_spec->dst, + ETHER_ADDR_LEN); + } + + i_eth_spec = eth_spec; + i_eth_mask = eth_mask; + break; + case RTE_FLOW_ITEM_TYPE_VLAN: + vlan_spec = + (const struct rte_flow_item_vlan *)item->spec; + vlan_mask = + (const struct rte_flow_item_vlan *)item->mask; + + if (!(vlan_spec && vlan_mask)) { + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ITEM, + item, + "Invalid vlan item"); + return -rte_errno; + } + + if (!vlan_flag) { + o_vlan_spec = vlan_spec; + vlan_flag = 1; + } else { + i_vlan_spec = vlan_spec; + vlan_flag = 0; + } + break; + + default: + break; + } + } + + /* Check specification and mask to get the filter type */ + if (vlan_spec && vlan_mask && + (vlan_mask->tci == rte_cpu_to_be_16(I40E_TCI_MASK))) { + /* If there's inner vlan */ + if (vlan_flag) + filter->inner_vlan = rte_be_to_cpu_16(o_vlan_spec->tci) + & I40E_TCI_MASK; + else { + /* There is an inner and outer vlan */ + filter->outer_vlan = rte_be_to_cpu_16(o_vlan_spec->tci) + & I40E_TCI_MASK; + filter->inner_vlan = rte_be_to_cpu_16(i_vlan_spec->tci) + & I40E_TCI_MASK; + } + + if (i_eth_spec && i_eth_mask) + filter->filter_type = + I40E_TUNNEL_FILTER_CUSTOM_QINQ; + else { + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ITEM, + NULL, + "Invalid filter type"); + return -rte_errno; + } + } else if ((!vlan_spec && !vlan_mask) || + (vlan_spec && vlan_mask && vlan_mask->tci == 0x0)) { + if (i_eth_spec && i_eth_mask) { + filter->filter_type = I40E_TUNNEL_FILTER_CUSTOM_QINQ; + } else { + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ITEM, NULL, + "Invalid filter type"); + return -rte_errno; + } + } else { + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ITEM, NULL, + "Not supported by tunnel filter."); + return -rte_errno; + } + + filter->tunnel_type = I40E_TUNNEL_TYPE_QINQ; + + return 0; +} + +static int +i40e_flow_parse_qinq_filter(struct rte_eth_dev *dev, + const struct rte_flow_attr *attr, + const struct rte_flow_item pattern[], + const struct rte_flow_action actions[], + struct rte_flow_error *error, + union i40e_filter_t *filter) +{ + struct i40e_tunnel_filter_conf *tunnel_filter = + &filter->consistent_tunnel_filter; + int ret; + + ret = i40e_flow_parse_qinq_pattern(dev, pattern, + error, tunnel_filter); + if (ret) + return ret; + + ret = i40e_flow_parse_tunnel_action(dev, actions, error, tunnel_filter); + if (ret) + return ret; + + ret = i40e_flow_parse_attr(attr, error); + if (ret) + return ret; + + cons_filter_type = RTE_ETH_FILTER_TUNNEL; + + return ret; +} + +static int i40e_flow_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr, const struct rte_flow_item pattern[],