From patchwork Mon Mar 6 13:05:08 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Rybchenko X-Patchwork-Id: 21478 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [IPv6:::1]) by dpdk.org (Postfix) with ESMTP id 06E7E108A; Mon, 6 Mar 2017 14:05:28 +0100 (CET) Received: from nbfkord-smmo02.seg.att.com (nbfkord-smmo02.seg.att.com [209.65.160.78]) by dpdk.org (Postfix) with ESMTP id 8217C952 for ; Mon, 6 Mar 2017 14:05:25 +0100 (CET) Received: from unknown [12.187.104.26] by nbfkord-smmo02.seg.att.com(mxl_mta-7.2.4-7) with SMTP id 29e5db85.0.1202591.00-2312.3367543.nbfkord-smmo02.seg.att.com (envelope-from ); Mon, 06 Mar 2017 13:05:25 +0000 (UTC) X-MXL-Hash: 58bd5e9557886904-30030615f31a1a2a2dbc822d1240298e621bd1b8 Received: from ocex03.SolarFlarecom.com (10.20.40.36) by ocex03.SolarFlarecom.com (10.20.40.36) with Microsoft SMTP Server (TLS) id 15.0.1044.25; Mon, 6 Mar 2017 05:05:18 -0800 Received: from opal.uk.solarflarecom.com (10.17.10.1) by ocex03.SolarFlarecom.com (10.20.40.36) with Microsoft SMTP Server (TLS) id 15.0.1044.25 via Frontend Transport; Mon, 6 Mar 2017 05:05:17 -0800 Received: from uklogin.uk.solarflarecom.com (uklogin.uk.solarflarecom.com [10.17.10.10]) by opal.uk.solarflarecom.com (8.13.8/8.13.8) with ESMTP id v26D5GIF026540 for ; Mon, 6 Mar 2017 13:05:16 GMT Received: from uklogin.uk.solarflarecom.com (localhost.localdomain [127.0.0.1]) by uklogin.uk.solarflarecom.com (8.13.8/8.13.8) with ESMTP id v26D5GE7032291 for ; Mon, 6 Mar 2017 13:05:16 GMT From: Andrew Rybchenko To: Date: Mon, 6 Mar 2017 13:05:08 +0000 Message-ID: <1488805509-32237-1-git-send-email-arybchenko@solarflare.com> X-Mailer: git-send-email 1.8.2.3 MIME-Version: 1.0 X-AnalysisOut: [v=2.1 cv=T6yKOq+Q c=1 sm=1 tr=0 a=8BlWFWvVlq5taO8ncb8nKg==] X-AnalysisOut: [:17 a=6Iz7jQTuP9IA:10 a=zRKbQ67AAAAA:8 a=9Ri33N3nQ9AG3LkAa] X-AnalysisOut: [XkA:9 a=ewDtYHk4Z6vVR8Hi:21 a=ROtUoFVNx-jht5ts:21 a=oClbA6] X-AnalysisOut: [zsTVMJsnUP:21 a=PA03WX8tBzeizutn5_OT:22] X-Spam: [F=0.4426073896; CM=0.500; S=0.442(2015072901)] X-MAIL-FROM: X-SOURCE-IP: [12.187.104.26] Subject: [dpdk-dev] [PATCH 1/2] net/sfc/base: separate limitations on Tx DMA descriptors X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Siena has limitation on maximum byte count and 4k boundary crosssing (which is stricter than maximum byte count). EF10 has limitation on maximum byte count only. Fixes: f7dc06bf35f2 ("net/sfc/base: import 5xxx/6xxx family support") Fixes: e7cd430c864f ("net/sfc/base: import SFN7xxx family support") Fixes: 94190e3543bf ("net/sfc/base: import SFN8xxx family support") Signed-off-by: Andrew Rybchenko --- drivers/net/sfc/base/ef10_tx.c | 9 +++++---- drivers/net/sfc/base/efx.h | 7 +++++++ drivers/net/sfc/base/efx_tx.c | 16 ++++++++++++---- drivers/net/sfc/base/hunt_nic.c | 4 ++++ drivers/net/sfc/base/medford_nic.c | 4 ++++ drivers/net/sfc/base/siena_nic.c | 4 ++++ 6 files changed, 36 insertions(+), 8 deletions(-) diff --git a/drivers/net/sfc/base/ef10_tx.c b/drivers/net/sfc/base/ef10_tx.c index aa19cce..0f48a6c 100644 --- a/drivers/net/sfc/base/ef10_tx.c +++ b/drivers/net/sfc/base/ef10_tx.c @@ -435,8 +435,9 @@ ef10_tx_qpost( size_t offset; efx_qword_t qword; - /* Fragments must not span 4k boundaries. */ - EFSYS_ASSERT(P2ROUNDUP(addr + 1, 4096) >= (addr + size)); + /* No limitations on boundary crossing */ + EFSYS_ASSERT(size <= + etp->et_enp->en_nic_cfg.enc_tx_dma_desc_size_max); id = added++ & etp->et_mask; offset = id * sizeof (efx_qword_t); @@ -551,8 +552,8 @@ ef10_tx_qdesc_dma_create( __in boolean_t eop, __out efx_desc_t *edp) { - /* Fragments must not span 4k boundaries. */ - EFSYS_ASSERT(P2ROUNDUP(addr + 1, 4096) >= addr + size); + /* No limitations on boundary crossing */ + EFSYS_ASSERT(size <= etp->et_enp->en_nic_cfg.enc_tx_dma_desc_size_max); EFSYS_PROBE4(tx_desc_dma_create, unsigned int, etp->et_index, efsys_dma_addr_t, addr, diff --git a/drivers/net/sfc/base/efx.h b/drivers/net/sfc/base/efx.h index 0815d7a..ac702f3 100644 --- a/drivers/net/sfc/base/efx.h +++ b/drivers/net/sfc/base/efx.h @@ -1154,6 +1154,13 @@ typedef struct efx_nic_cfg_s { uint32_t enc_rx_batch_max; /* Number of rx descriptors the hardware requires for a push. */ uint32_t enc_rx_push_align; + /* Maximum amount of data in DMA descriptor */ + uint32_t enc_tx_dma_desc_size_max; + /* + * Boundary which DMA descriptor data must not cross or 0 if no + * limitation. + */ + uint32_t enc_tx_dma_desc_boundary; /* * Maximum number of bytes into the packet the TCP header can start for * the hardware to apply TSO packet edits. diff --git a/drivers/net/sfc/base/efx_tx.c b/drivers/net/sfc/base/efx_tx.c index 0d47390..ceb2920 100644 --- a/drivers/net/sfc/base/efx_tx.c +++ b/drivers/net/sfc/base/efx_tx.c @@ -745,8 +745,12 @@ siena_tx_qpost( size_t size = ebp->eb_size; efsys_dma_addr_t end = start + size; - /* Fragments must not span 4k boundaries. */ - EFSYS_ASSERT(P2ROUNDUP(start + 1, 4096) >= end); + /* + * Fragments must not span 4k boundaries. + * Here it is a stricter requirement than the maximum length. + */ + EFSYS_ASSERT(P2ROUNDUP(start + 1, + etp->et_enp->en_nic_cfg.enc_tx_dma_desc_boundary) >= end); EFX_TX_DESC(etp, start, size, ebp->eb_eop, added); } @@ -1005,8 +1009,12 @@ siena_tx_qdesc_dma_create( __in boolean_t eop, __out efx_desc_t *edp) { - /* Fragments must not span 4k boundaries. */ - EFSYS_ASSERT(P2ROUNDUP(addr + 1, 4096) >= addr + size); + /* + * Fragments must not span 4k boundaries. + * Here it is a stricter requirement than the maximum length. + */ + EFSYS_ASSERT(P2ROUNDUP(addr + 1, + etp->et_enp->en_nic_cfg.enc_tx_dma_desc_boundary) >= addr + size); EFSYS_PROBE4(tx_desc_dma_create, unsigned int, etp->et_index, efsys_dma_addr_t, addr, diff --git a/drivers/net/sfc/base/hunt_nic.c b/drivers/net/sfc/base/hunt_nic.c index c2c4d74..addbf1c 100644 --- a/drivers/net/sfc/base/hunt_nic.c +++ b/drivers/net/sfc/base/hunt_nic.c @@ -301,6 +301,10 @@ hunt_board_cfg( /* Alignment for WPTR updates */ encp->enc_rx_push_align = EF10_RX_WPTR_ALIGN; + encp->enc_tx_dma_desc_size_max = EFX_MASK32(ESF_DZ_RX_KER_BYTE_CNT); + /* No boundary crossing limits */ + encp->enc_tx_dma_desc_boundary = 0; + /* * Set resource limits for MC_CMD_ALLOC_VIS. Note that we cannot use * MC_CMD_GET_RESOURCE_LIMITS here as that reports the available diff --git a/drivers/net/sfc/base/medford_nic.c b/drivers/net/sfc/base/medford_nic.c index 6ad68c6..07afac1 100644 --- a/drivers/net/sfc/base/medford_nic.c +++ b/drivers/net/sfc/base/medford_nic.c @@ -298,6 +298,10 @@ medford_board_cfg( /* Alignment for WPTR updates */ encp->enc_rx_push_align = EF10_RX_WPTR_ALIGN; + encp->enc_tx_dma_desc_size_max = EFX_MASK32(ESF_DZ_RX_KER_BYTE_CNT); + /* No boundary crossing limits */ + encp->enc_tx_dma_desc_boundary = 0; + /* * Set resource limits for MC_CMD_ALLOC_VIS. Note that we cannot use * MC_CMD_GET_RESOURCE_LIMITS here as that reports the available diff --git a/drivers/net/sfc/base/siena_nic.c b/drivers/net/sfc/base/siena_nic.c index 1f8c4e7..129b854 100644 --- a/drivers/net/sfc/base/siena_nic.c +++ b/drivers/net/sfc/base/siena_nic.c @@ -135,6 +135,10 @@ siena_board_cfg( /* Alignment for WPTR updates */ encp->enc_rx_push_align = 1; + encp->enc_tx_dma_desc_size_max = EFX_MASK32(FSF_AZ_TX_KER_BYTE_COUNT); + /* Fragments must not span 4k boundaries. */ + encp->enc_tx_dma_desc_boundary = 4096; + /* Resource limits */ rc = efx_mcdi_get_resource_limits(enp, &nevq, &nrxq, &ntxq); if (rc != 0) {