From patchwork Sun Nov 6 16:55:10 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wenzhuo Lu X-Patchwork-Id: 16958 Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [IPv6:::1]) by dpdk.org (Postfix) with ESMTP id B991711C5; Mon, 7 Nov 2016 02:04:18 +0100 (CET) Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by dpdk.org (Postfix) with ESMTP id 47D2AE07 for ; Mon, 7 Nov 2016 02:04:16 +0100 (CET) Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga104.fm.intel.com with ESMTP; 06 Nov 2016 17:04:15 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.31,604,1473145200"; d="scan'208";a="898441745" Received: from dpdk26.sh.intel.com ([10.239.128.228]) by orsmga003.jf.intel.com with ESMTP; 06 Nov 2016 17:04:14 -0800 From: Wenzhuo Lu To: dev@dpdk.org Cc: Wenzhuo Lu Date: Sun, 6 Nov 2016 11:55:10 -0500 Message-Id: <1478451310-104316-1-git-send-email-wenzhuo.lu@intel.com> X-Mailer: git-send-email 1.9.3 Subject: [dpdk-dev] [PATCH] ixgbe: fix wrong VF TX registers X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" The VF TX registers are using PF's addresses by mistake, correct them. Fixes: 0198848a47f5 ("ixgbe: add access to specific device info") Reported-by: Xuekun Hu Signed-off-by: Wenzhuo Lu --- drivers/net/ixgbe/ixgbe_regs.h | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/net/ixgbe/ixgbe_regs.h b/drivers/net/ixgbe/ixgbe_regs.h index c7457a6..4af035f 100644 --- a/drivers/net/ixgbe/ixgbe_regs.h +++ b/drivers/net/ixgbe/ixgbe_regs.h @@ -193,14 +193,14 @@ static struct reg_info ixgbe_regs_tx[] = { }; static const struct reg_info ixgbevf_regs_tx[] = { - {IXGBE_TDBAL(0), 4, 0x40, "IXGBE_TDBAL"}, - {IXGBE_TDBAH(0), 4, 0x40, "IXGBE_TDBAH"}, - {IXGBE_TDLEN(0), 4, 0x40, "IXGBE_TDLEN"}, - {IXGBE_TDH(0), 4, 0x40, "IXGBE_TDH"}, - {IXGBE_TDT(0), 4, 0x40, "IXGBE_TDT"}, - {IXGBE_TXDCTL(0), 4, 0x40, "IXGBE_TXDCTL"}, - {IXGBE_TDWBAL(0), 4, 0x40, "IXGBE_TDWBAL"}, - {IXGBE_TDWBAH(0), 4, 0x40, "IXGBE_TDWBAH"}, + {IXGBE_VFTDBAL(0), 4, 0x40, "IXGBE_VFTDBAL"}, + {IXGBE_VFTDBAH(0), 4, 0x40, "IXGBE_VFTDBAH"}, + {IXGBE_VFTDLEN(0), 4, 0x40, "IXGBE_VFTDLEN"}, + {IXGBE_VFTDH(0), 4, 0x40, "IXGBE_VFTDH"}, + {IXGBE_VFTDT(0), 4, 0x40, "IXGBE_VFTDT"}, + {IXGBE_VFTXDCTL(0), 4, 0x40, "IXGBE_VFTXDCTL"}, + {IXGBE_VFTDWBAL(0), 4, 0x40, "IXGBE_VFTDWBAL"}, + {IXGBE_VFTDWBAH(0), 4, 0x40, "IXGBE_VFTDWBAH"}, {0, 0, 0, ""} };