diff --git a/drivers/net/qede/base/common_hsi.h b/drivers/net/qede/base/common_hsi.h
index 4574800..b431c78 100644
--- a/drivers/net/qede/base/common_hsi.h
+++ b/drivers/net/qede/base/common_hsi.h
@@ -8,12 +8,89 @@
 
 #ifndef __COMMON_HSI__
 #define __COMMON_HSI__
+/********************************/
+/* PROTOCOL COMMON FW CONSTANTS */
+/********************************/
+
+/* Temporarily here should be added to HSI automatically by resource allocation
+ * tool.
+ */
+#define T_TEST_AGG_INT_TEMP    6
+#define	M_TEST_AGG_INT_TEMP    8
+#define	U_TEST_AGG_INT_TEMP    6
+#define	X_TEST_AGG_INT_TEMP    14
+#define	Y_TEST_AGG_INT_TEMP    4
+#define	P_TEST_AGG_INT_TEMP    4
+
+#define X_FINAL_CLEANUP_AGG_INT  1
+
+#define EVENT_RING_PAGE_SIZE_BYTES          4096
+
+#define NUM_OF_GLOBAL_QUEUES				128
+#define COMMON_QUEUE_ENTRY_MAX_BYTE_SIZE	64
+
+#define ISCSI_CDU_TASK_SEG_TYPE       0
+#define FCOE_CDU_TASK_SEG_TYPE        0
+#define RDMA_CDU_TASK_SEG_TYPE        1
+
+#define FW_ASSERT_GENERAL_ATTN_IDX    32
+
+#define MAX_PINNED_CCFC			32
+
+#define EAGLE_ENG1_WORKAROUND_NIG_FLOWCTRL_MODE	3
+
+/* Queue Zone sizes in bytes */
+#define TSTORM_QZONE_SIZE    8	 /*tstorm_scsi_queue_zone*/
+#define MSTORM_QZONE_SIZE    16  /*mstorm_eth_queue_zone. Used only for RX
+				  *producer of VFs in backward compatibility
+				  *mode.
+				  */
+#define USTORM_QZONE_SIZE    8	 /*ustorm_eth_queue_zone*/
+#define XSTORM_QZONE_SIZE    8	 /*xstorm_eth_queue_zone*/
+#define YSTORM_QZONE_SIZE    0
+#define PSTORM_QZONE_SIZE    0
+
+/*Log of mstorm default VF zone size.*/
+#define MSTORM_VF_ZONE_DEFAULT_SIZE_LOG       7
+/*Maximum number of RX queues that can be allocated to VF by default*/
+#define ETH_MAX_NUM_RX_QUEUES_PER_VF_DEFAULT  16
+/*Maximum number of RX queues that can be allocated to VF with doubled VF zone
+ * size. Up to 96 VF supported in this mode
+ */
+#define ETH_MAX_NUM_RX_QUEUES_PER_VF_DOUBLE   48
+/*Maximum number of RX queues that can be allocated to VF with 4 VF zone size.
+ * Up to 48 VF supported in this mode
+ */
+#define ETH_MAX_NUM_RX_QUEUES_PER_VF_QUAD     112
+
+
+/********************************/
+/* CORE (LIGHT L2) FW CONSTANTS */
+/********************************/
+
+#define CORE_LL2_MAX_RAMROD_PER_CON				8
+#define CORE_LL2_TX_BD_PAGE_SIZE_BYTES			4096
+#define CORE_LL2_RX_BD_PAGE_SIZE_BYTES			4096
+#define CORE_LL2_RX_CQE_PAGE_SIZE_BYTES			4096
+#define CORE_LL2_RX_NUM_NEXT_PAGE_BDS			1
+
+#define CORE_LL2_TX_MAX_BDS_PER_PACKET				12
+
+#define CORE_SPQE_PAGE_SIZE_BYTES                       4096
+
+#define MAX_NUM_LL2_RX_QUEUES					32
+#define MAX_NUM_LL2_TX_STATS_COUNTERS			32
+
+
+/****************************************************************************/
+/* Include firmware version number only- do not add constants here to avoid */
+/* redundunt compilations                                                   */
+/****************************************************************************/
 
-#define CORE_SPQE_PAGE_SIZE_BYTES			4096
 
 #define FW_MAJOR_VERSION		8
-#define FW_MINOR_VERSION	7
-#define FW_REVISION_VERSION	7
+#define FW_MINOR_VERSION		10
+#define FW_REVISION_VERSION		9
 #define FW_ENGINEERING_VERSION	0
 
 /***********************/
@@ -21,70 +98,96 @@
 /***********************/
 
 /* PCI functions */
-#define MAX_NUM_PORTS_K2		(4)
-#define MAX_NUM_PORTS_BB		(2)
-#define MAX_NUM_PORTS			(MAX_NUM_PORTS_K2)
+#define MAX_NUM_PORTS_K2	(4)
+#define MAX_NUM_PORTS_BB	(2)
+#define MAX_NUM_PORTS		(MAX_NUM_PORTS_K2)
 
-#define MAX_NUM_PFS_K2			(16)
-#define MAX_NUM_PFS_BB			(8)
-#define MAX_NUM_PFS				(MAX_NUM_PFS_K2)
-#define MAX_NUM_OF_PFS_IN_CHIP	(16) /* On both engines */
+#define MAX_NUM_PFS_K2	(16)
+#define MAX_NUM_PFS_BB	(8)
+#define MAX_NUM_PFS	(MAX_NUM_PFS_K2)
+#define MAX_NUM_OF_PFS_IN_CHIP (16) /* On both engines */
 
-#define MAX_NUM_VFS_K2			(192)
-#define MAX_NUM_VFS_BB			(120)
-#define MAX_NUM_VFS				(MAX_NUM_VFS_K2)
+#define MAX_NUM_VFS_K2	(192)
+#define MAX_NUM_VFS_BB	(120)
+#define MAX_NUM_VFS	(MAX_NUM_VFS_K2)
 
 #define MAX_NUM_FUNCTIONS_BB	(MAX_NUM_PFS_BB + MAX_NUM_VFS_BB)
-#define MAX_NUM_FUNCTIONS		(MAX_NUM_PFS + MAX_NUM_VFS)
+#define MAX_NUM_FUNCTIONS_K2	(MAX_NUM_PFS_K2 + MAX_NUM_VFS_K2)
+#define MAX_NUM_FUNCTIONS	(MAX_NUM_PFS + MAX_NUM_VFS)
 
+/* in both BB and K2, the VF number starts from 16. so for arrays containing all
+ * possible PFs and VFs - we need a constant for this size
+ */
 #define MAX_FUNCTION_NUMBER_BB	(MAX_NUM_PFS + MAX_NUM_VFS_BB)
-#define MAX_FUNCTION_NUMBER		(MAX_NUM_PFS + MAX_NUM_VFS)
+#define MAX_FUNCTION_NUMBER_K2	(MAX_NUM_PFS + MAX_NUM_VFS_K2)
+#define MAX_FUNCTION_NUMBER	(MAX_NUM_PFS + MAX_NUM_VFS)
 
-#define MAX_NUM_VPORTS_K2		(208)
-#define MAX_NUM_VPORTS_BB		(160)
-#define MAX_NUM_VPORTS			(MAX_NUM_VPORTS_K2)
+#define MAX_NUM_VPORTS_K2	(208)
+#define MAX_NUM_VPORTS_BB	(160)
+#define MAX_NUM_VPORTS		(MAX_NUM_VPORTS_K2)
 
 #define MAX_NUM_L2_QUEUES_K2	(320)
 #define MAX_NUM_L2_QUEUES_BB	(256)
-#define MAX_NUM_L2_QUEUES		(MAX_NUM_L2_QUEUES_K2)
+#define MAX_NUM_L2_QUEUES	(MAX_NUM_L2_QUEUES_K2)
 
 /* Traffic classes in network-facing blocks (PBF, BTB, NIG, BRB, PRS and QM) */
+/* 4-Port K2. */
 #define NUM_PHYS_TCS_4PORT_K2	(4)
-#define NUM_OF_PHYS_TCS			(8)
+#define NUM_OF_PHYS_TCS		(8)
 
-#define NUM_TCS_4PORT_K2		(NUM_PHYS_TCS_4PORT_K2 + 1)
-#define NUM_OF_TCS				(NUM_OF_PHYS_TCS + 1)
+#define NUM_TCS_4PORT_K2	(NUM_PHYS_TCS_4PORT_K2 + 1)
+#define NUM_OF_TCS		(NUM_OF_PHYS_TCS + 1)
 
-#define LB_TC					(NUM_OF_PHYS_TCS)
+#define LB_TC			(NUM_OF_PHYS_TCS)
 
 /* Num of possible traffic priority values */
-#define NUM_OF_PRIO				(8)
+#define NUM_OF_PRIO		(8)
 
-#define MAX_NUM_VOQS_K2			(NUM_TCS_4PORT_K2 * MAX_NUM_PORTS_K2)
-#define MAX_NUM_VOQS_BB         (NUM_OF_TCS * MAX_NUM_PORTS_BB)
-#define MAX_NUM_VOQS			(MAX_NUM_VOQS_K2)
-#define MAX_PHYS_VOQS			(NUM_OF_PHYS_TCS * MAX_NUM_PORTS_BB)
+#define MAX_NUM_VOQS_K2		(NUM_TCS_4PORT_K2 * MAX_NUM_PORTS_K2)
+#define MAX_NUM_VOQS_BB		(NUM_OF_TCS * MAX_NUM_PORTS_BB)
+#define MAX_NUM_VOQS		(MAX_NUM_VOQS_K2)
+#define MAX_PHYS_VOQS		(NUM_OF_PHYS_TCS * MAX_NUM_PORTS_BB)
 
 /* CIDs */
-#define NUM_OF_CONNECTION_TYPES (8)
-#define NUM_OF_LCIDS			(320)
-#define NUM_OF_LTIDS			(320)
-
+#define NUM_OF_CONNECTION_TYPES	(8)
+#define NUM_OF_LCIDS		(320)
+#define NUM_OF_LTIDS		(320)
+
+/* Clock values */
+#define MASTER_CLK_FREQ_E4		(375e6)
+#define STORM_CLK_FREQ_E4		(1000e6)
+#define CLK25M_CLK_FREQ_E4		(25e6)
+
+/* Global PXP windows (GTT) */
+#define NUM_OF_GTT			19
+#define GTT_DWORD_SIZE_BITS	10
+#define GTT_BYTE_SIZE_BITS	(GTT_DWORD_SIZE_BITS + 2)
+#define GTT_DWORD_SIZE		(1 << GTT_DWORD_SIZE_BITS)
+
+/* Tools Version */
+#define TOOLS_VERSION 10
 /*****************/
 /* CDU CONSTANTS */
 /*****************/
 
-#define CDU_SEG_TYPE_OFFSET_REG_TYPE_SHIFT		(17)
-#define CDU_SEG_TYPE_OFFSET_REG_OFFSET_MASK		(0x1ffff)
+#define CDU_SEG_TYPE_OFFSET_REG_TYPE_SHIFT              (17)
+#define CDU_SEG_TYPE_OFFSET_REG_OFFSET_MASK             (0x1ffff)
+
+#define CDU_VF_FL_SEG_TYPE_OFFSET_REG_TYPE_SHIFT	(12)
+#define CDU_VF_FL_SEG_TYPE_OFFSET_REG_OFFSET_MASK	(0xfff)
+
 
 /*****************/
 /* DQ CONSTANTS  */
 /*****************/
 
 /* DEMS */
-#define	DQ_DEMS_LEGACY						0
+#define DQ_DEMS_LEGACY			0
+#define DQ_DEMS_TOE_MORE_TO_SEND			3
+#define DQ_DEMS_TOE_LOCAL_ADV_WND			4
+#define DQ_DEMS_ROCE_CQ_CONS				7
 
-/* XCM agg val selection */
+/* XCM agg val selection (HW) */
 #define DQ_XCM_AGG_VAL_SEL_WORD2  0
 #define DQ_XCM_AGG_VAL_SEL_WORD3  1
 #define DQ_XCM_AGG_VAL_SEL_WORD4  2
@@ -94,7 +197,7 @@
 #define DQ_XCM_AGG_VAL_SEL_REG5   6
 #define DQ_XCM_AGG_VAL_SEL_REG6   7
 
-/* XCM agg val selection */
+/* XCM agg val selection (FW) */
 #define DQ_XCM_ETH_EDPM_NUM_BDS_CMD \
 	DQ_XCM_AGG_VAL_SEL_WORD2
 #define DQ_XCM_ETH_TX_BD_CONS_CMD \
@@ -107,9 +210,50 @@
 	DQ_XCM_AGG_VAL_SEL_WORD4
 #define DQ_XCM_CORE_SPQ_PROD_CMD \
 	DQ_XCM_AGG_VAL_SEL_WORD4
-#define DQ_XCM_ETH_GO_TO_BD_CONS_CMD        DQ_XCM_AGG_VAL_SEL_WORD5
-
-/* XCM agg counter flag selection */
+#define DQ_XCM_ETH_GO_TO_BD_CONS_CMD            DQ_XCM_AGG_VAL_SEL_WORD5
+#define DQ_XCM_FCOE_SQ_CONS_CMD             DQ_XCM_AGG_VAL_SEL_WORD3
+#define DQ_XCM_FCOE_SQ_PROD_CMD             DQ_XCM_AGG_VAL_SEL_WORD4
+#define DQ_XCM_FCOE_X_FERQ_PROD_CMD         DQ_XCM_AGG_VAL_SEL_WORD5
+#define DQ_XCM_ISCSI_SQ_CONS_CMD            DQ_XCM_AGG_VAL_SEL_WORD3
+#define DQ_XCM_ISCSI_SQ_PROD_CMD            DQ_XCM_AGG_VAL_SEL_WORD4
+#define DQ_XCM_ISCSI_MORE_TO_SEND_SEQ_CMD   DQ_XCM_AGG_VAL_SEL_REG3
+#define DQ_XCM_ISCSI_EXP_STAT_SN_CMD        DQ_XCM_AGG_VAL_SEL_REG6
+#define DQ_XCM_ROCE_SQ_PROD_CMD             DQ_XCM_AGG_VAL_SEL_WORD4
+#define DQ_XCM_TOE_TX_BD_PROD_CMD           DQ_XCM_AGG_VAL_SEL_WORD4
+#define DQ_XCM_TOE_MORE_TO_SEND_SEQ_CMD     DQ_XCM_AGG_VAL_SEL_REG3
+#define DQ_XCM_TOE_LOCAL_ADV_WND_SEQ_CMD    DQ_XCM_AGG_VAL_SEL_REG4
+
+/* UCM agg val selection (HW) */
+#define DQ_UCM_AGG_VAL_SEL_WORD0  0
+#define DQ_UCM_AGG_VAL_SEL_WORD1  1
+#define DQ_UCM_AGG_VAL_SEL_WORD2  2
+#define DQ_UCM_AGG_VAL_SEL_WORD3  3
+#define DQ_UCM_AGG_VAL_SEL_REG0   4
+#define DQ_UCM_AGG_VAL_SEL_REG1   5
+#define DQ_UCM_AGG_VAL_SEL_REG2   6
+#define DQ_UCM_AGG_VAL_SEL_REG3   7
+
+/* UCM agg val selection (FW) */
+#define DQ_UCM_ETH_PMD_TX_CONS_CMD			DQ_UCM_AGG_VAL_SEL_WORD2
+#define DQ_UCM_ETH_PMD_RX_CONS_CMD			DQ_UCM_AGG_VAL_SEL_WORD3
+#define DQ_UCM_ROCE_CQ_CONS_CMD				DQ_UCM_AGG_VAL_SEL_REG0
+#define DQ_UCM_ROCE_CQ_PROD_CMD				DQ_UCM_AGG_VAL_SEL_REG2
+
+/* TCM agg val selection (HW) */
+#define DQ_TCM_AGG_VAL_SEL_WORD0  0
+#define DQ_TCM_AGG_VAL_SEL_WORD1  1
+#define DQ_TCM_AGG_VAL_SEL_WORD2  2
+#define DQ_TCM_AGG_VAL_SEL_WORD3  3
+#define DQ_TCM_AGG_VAL_SEL_REG1   4
+#define DQ_TCM_AGG_VAL_SEL_REG2   5
+#define DQ_TCM_AGG_VAL_SEL_REG6   6
+#define DQ_TCM_AGG_VAL_SEL_REG9   7
+
+/* TCM agg val selection (FW) */
+#define DQ_TCM_L2B_BD_PROD_CMD				DQ_TCM_AGG_VAL_SEL_WORD1
+#define DQ_TCM_ROCE_RQ_PROD_CMD				DQ_TCM_AGG_VAL_SEL_WORD0
+
+/* XCM agg counter flag selection (HW) */
 #define DQ_XCM_AGG_FLG_SHIFT_BIT14  0
 #define DQ_XCM_AGG_FLG_SHIFT_BIT15  1
 #define DQ_XCM_AGG_FLG_SHIFT_CF12   2
@@ -119,7 +263,7 @@
 #define DQ_XCM_AGG_FLG_SHIFT_CF22   6
 #define DQ_XCM_AGG_FLG_SHIFT_CF23   7
 
-/* XCM agg counter flag selection */
+/* XCM agg counter flag selection (FW) */
 #define DQ_XCM_ETH_DQ_CF_CMD		(1 << \
 					DQ_XCM_AGG_FLG_SHIFT_CF18)
 #define DQ_XCM_CORE_DQ_CF_CMD		(1 << \
@@ -134,28 +278,109 @@
 					DQ_XCM_AGG_FLG_SHIFT_CF22)
 #define DQ_XCM_ETH_TPH_EN_CMD		(1 << \
 					DQ_XCM_AGG_FLG_SHIFT_CF23)
+#define DQ_XCM_FCOE_SLOW_PATH_CMD           (1 << DQ_XCM_AGG_FLG_SHIFT_CF22)
+#define DQ_XCM_ISCSI_DQ_FLUSH_CMD           (1 << DQ_XCM_AGG_FLG_SHIFT_CF19)
+#define DQ_XCM_ISCSI_SLOW_PATH_CMD          (1 << DQ_XCM_AGG_FLG_SHIFT_CF22)
+#define DQ_XCM_ISCSI_PROC_ONLY_CLEANUP_CMD  (1 << DQ_XCM_AGG_FLG_SHIFT_CF23)
+#define DQ_XCM_TOE_DQ_FLUSH_CMD             (1 << DQ_XCM_AGG_FLG_SHIFT_CF19)
+#define DQ_XCM_TOE_SLOW_PATH_CMD            (1 << DQ_XCM_AGG_FLG_SHIFT_CF22)
+
+/* UCM agg counter flag selection (HW) */
+#define DQ_UCM_AGG_FLG_SHIFT_CF0       0
+#define DQ_UCM_AGG_FLG_SHIFT_CF1       1
+#define DQ_UCM_AGG_FLG_SHIFT_CF3       2
+#define DQ_UCM_AGG_FLG_SHIFT_CF4       3
+#define DQ_UCM_AGG_FLG_SHIFT_CF5       4
+#define DQ_UCM_AGG_FLG_SHIFT_CF6       5
+#define DQ_UCM_AGG_FLG_SHIFT_RULE0EN   6
+#define DQ_UCM_AGG_FLG_SHIFT_RULE1EN   7
+
+/* UCM agg counter flag selection (FW) */
+#define DQ_UCM_ETH_PMD_TX_ARM_CMD           (1 << DQ_UCM_AGG_FLG_SHIFT_CF4)
+#define DQ_UCM_ETH_PMD_RX_ARM_CMD           (1 << DQ_UCM_AGG_FLG_SHIFT_CF5)
+#define DQ_UCM_ROCE_CQ_ARM_SE_CF_CMD        (1 << DQ_UCM_AGG_FLG_SHIFT_CF4)
+#define DQ_UCM_ROCE_CQ_ARM_CF_CMD           (1 << DQ_UCM_AGG_FLG_SHIFT_CF5)
+#define DQ_UCM_TOE_TIMER_STOP_ALL_CMD       (1 << DQ_UCM_AGG_FLG_SHIFT_CF3)
+#define DQ_UCM_TOE_SLOW_PATH_CF_CMD         (1 << DQ_UCM_AGG_FLG_SHIFT_CF4)
+#define DQ_UCM_TOE_DQ_CF_CMD                (1 << DQ_UCM_AGG_FLG_SHIFT_CF5)
+
+/* TCM agg counter flag selection (HW) */
+#define DQ_TCM_AGG_FLG_SHIFT_CF0  0
+#define DQ_TCM_AGG_FLG_SHIFT_CF1  1
+#define DQ_TCM_AGG_FLG_SHIFT_CF2  2
+#define DQ_TCM_AGG_FLG_SHIFT_CF3  3
+#define DQ_TCM_AGG_FLG_SHIFT_CF4  4
+#define DQ_TCM_AGG_FLG_SHIFT_CF5  5
+#define DQ_TCM_AGG_FLG_SHIFT_CF6  6
+#define DQ_TCM_AGG_FLG_SHIFT_CF7  7
+
+/* TCM agg counter flag selection (FW) */
+#define DQ_TCM_FCOE_FLUSH_Q0_CMD            (1 << DQ_TCM_AGG_FLG_SHIFT_CF1)
+#define DQ_TCM_FCOE_DUMMY_TIMER_CMD         (1 << DQ_TCM_AGG_FLG_SHIFT_CF2)
+#define DQ_TCM_FCOE_TIMER_STOP_ALL_CMD      (1 << DQ_TCM_AGG_FLG_SHIFT_CF3)
+#define DQ_TCM_ISCSI_FLUSH_Q0_CMD           (1 << DQ_TCM_AGG_FLG_SHIFT_CF1)
+#define DQ_TCM_ISCSI_TIMER_STOP_ALL_CMD     (1 << DQ_TCM_AGG_FLG_SHIFT_CF3)
+#define DQ_TCM_TOE_FLUSH_Q0_CMD             (1 << DQ_TCM_AGG_FLG_SHIFT_CF1)
+#define DQ_TCM_TOE_TIMER_STOP_ALL_CMD       (1 << DQ_TCM_AGG_FLG_SHIFT_CF3)
+#define DQ_TCM_IWARP_POST_RQ_CF_CMD         (1 << DQ_TCM_AGG_FLG_SHIFT_CF1)
+
+/* PWM address mapping */
+#define DQ_PWM_OFFSET_DPM_BASE				0x0
+#define DQ_PWM_OFFSET_DPM_END				0x27
+#define DQ_PWM_OFFSET_XCM16_BASE			0x40
+#define DQ_PWM_OFFSET_XCM32_BASE			0x44
+#define DQ_PWM_OFFSET_UCM16_BASE			0x48
+#define DQ_PWM_OFFSET_UCM32_BASE			0x4C
+#define DQ_PWM_OFFSET_UCM16_4				0x50
+#define DQ_PWM_OFFSET_TCM16_BASE			0x58
+#define DQ_PWM_OFFSET_TCM32_BASE			0x5C
+#define DQ_PWM_OFFSET_XCM_FLAGS				0x68
+#define DQ_PWM_OFFSET_UCM_FLAGS				0x69
+#define DQ_PWM_OFFSET_TCM_FLAGS				0x6B
+
+#define DQ_PWM_OFFSET_XCM_RDMA_SQ_PROD		(DQ_PWM_OFFSET_XCM16_BASE + 2)
+#define DQ_PWM_OFFSET_UCM_RDMA_CQ_CONS_32BIT	(DQ_PWM_OFFSET_UCM32_BASE)
+#define DQ_PWM_OFFSET_UCM_RDMA_CQ_CONS_16BIT	(DQ_PWM_OFFSET_UCM16_4)
+#define DQ_PWM_OFFSET_UCM_RDMA_INT_TIMEOUT	(DQ_PWM_OFFSET_UCM16_BASE + 2)
+#define DQ_PWM_OFFSET_UCM_RDMA_ARM_FLAGS	(DQ_PWM_OFFSET_UCM_FLAGS)
+#define DQ_PWM_OFFSET_TCM_ROCE_RQ_PROD		(DQ_PWM_OFFSET_TCM16_BASE + 1)
+#define DQ_PWM_OFFSET_TCM_IWARP_RQ_PROD		(DQ_PWM_OFFSET_TCM16_BASE + 3)
+
+#define DQ_REGION_SHIFT				        (12)
+
+/* DPM */
+#define	DQ_DPM_WQE_BUFF_SIZE			    (320)
+
+/* Conn type ranges */
+#define DQ_CONN_TYPE_RANGE_SHIFT			(4)
 
 /*****************/
 /* QM CONSTANTS  */
 /*****************/
 
 /* number of TX queues in the QM */
-#define MAX_QM_TX_QUEUES_K2			512
-#define MAX_QM_TX_QUEUES_BB			448
-#define MAX_QM_TX_QUEUES			MAX_QM_TX_QUEUES_K2
+#define MAX_QM_TX_QUEUES_K2	512
+#define MAX_QM_TX_QUEUES_BB	448
+#define MAX_QM_TX_QUEUES	MAX_QM_TX_QUEUES_K2
 
 /* number of Other queues in the QM */
-#define MAX_QM_OTHER_QUEUES_BB		64
-#define MAX_QM_OTHER_QUEUES_K2		128
-#define MAX_QM_OTHER_QUEUES			MAX_QM_OTHER_QUEUES_K2
+#define MAX_QM_OTHER_QUEUES_BB	64
+#define MAX_QM_OTHER_QUEUES_K2	128
+#define MAX_QM_OTHER_QUEUES	MAX_QM_OTHER_QUEUES_K2
 
 /* number of queues in a PF queue group */
-#define QM_PF_QUEUE_GROUP_SIZE		8
+#define QM_PF_QUEUE_GROUP_SIZE	8
+
+/* the size of a single queue element in bytes */
+#define QM_PQ_ELEMENT_SIZE			4
 
 /* base number of Tx PQs in the CM PQ representation.
  * should be used when storing PQ IDs in CM PQ registers and context
  */
-#define CM_TX_PQ_BASE               0x200
+#define CM_TX_PQ_BASE	0x200
+
+/* number of global Vport/QCN rate limiters */
+#define MAX_QM_GLOBAL_RLS			256
 
 /* QM registers data */
 #define QM_LINE_CRD_REG_WIDTH		16
@@ -164,7 +389,7 @@
 #define QM_BYTE_CRD_REG_SIGN_BIT	(1 << (QM_BYTE_CRD_REG_WIDTH - 1))
 #define QM_WFQ_CRD_REG_WIDTH		32
 #define QM_WFQ_CRD_REG_SIGN_BIT		(1 << (QM_WFQ_CRD_REG_WIDTH - 1))
-#define QM_RL_CRD_REG_WIDTH			32
+#define QM_RL_CRD_REG_WIDTH		32
 #define QM_RL_CRD_REG_SIGN_BIT		(1 << (QM_RL_CRD_REG_WIDTH - 1))
 
 /*****************/
@@ -177,114 +402,217 @@
 /* Number of Protocol Indices per Status Block */
 #define PIS_PER_SB    12
 
+/* fsm is stopped or not valid for this sb */
 #define CAU_HC_STOPPED_STATE	3
+/* fsm is working without interrupt coalescing for this sb*/
 #define CAU_HC_DISABLE_STATE	4
+/* fsm is working with interrupt coalescing for this sb*/
 #define CAU_HC_ENABLE_STATE	0
 
+
 /*****************/
 /* IGU CONSTANTS */
 /*****************/
 
-#define MAX_SB_PER_PATH_K2				(368)
-#define MAX_SB_PER_PATH_BB				(288)
+#define MAX_SB_PER_PATH_K2	(368)
+#define MAX_SB_PER_PATH_BB	(288)
 #define MAX_TOT_SB_PER_PATH \
 	MAX_SB_PER_PATH_K2
 
-#define MAX_SB_PER_PF_MIMD				129
-#define MAX_SB_PER_PF_SIMD				64
-#define MAX_SB_PER_VF					64
+#define MAX_SB_PER_PF_MIMD	129
+#define MAX_SB_PER_PF_SIMD	64
+#define MAX_SB_PER_VF		64
 
 /* Memory addresses on the BAR for the IGU Sub Block */
-#define IGU_MEM_BASE					0x0000
+#define IGU_MEM_BASE			0x0000
 
-#define IGU_MEM_MSIX_BASE				0x0000
-#define IGU_MEM_MSIX_UPPER				0x0101
-#define IGU_MEM_MSIX_RESERVED_UPPER			0x01ff
+#define IGU_MEM_MSIX_BASE		0x0000
+#define IGU_MEM_MSIX_UPPER		0x0101
+#define IGU_MEM_MSIX_RESERVED_UPPER	0x01ff
 
-#define IGU_MEM_PBA_MSIX_BASE				0x0200
-#define IGU_MEM_PBA_MSIX_UPPER				0x0202
-#define IGU_MEM_PBA_MSIX_RESERVED_UPPER			0x03ff
+#define IGU_MEM_PBA_MSIX_BASE		0x0200
+#define IGU_MEM_PBA_MSIX_UPPER		0x0202
+#define IGU_MEM_PBA_MSIX_RESERVED_UPPER	0x03ff
 
-#define IGU_CMD_INT_ACK_BASE				0x0400
+#define IGU_CMD_INT_ACK_BASE		0x0400
 #define IGU_CMD_INT_ACK_UPPER		(IGU_CMD_INT_ACK_BASE +	\
 					 MAX_TOT_SB_PER_PATH -	\
 					 1)
-#define IGU_CMD_INT_ACK_RESERVED_UPPER			0x05ff
+#define IGU_CMD_INT_ACK_RESERVED_UPPER	0x05ff
 
-#define IGU_CMD_ATTN_BIT_UPD_UPPER			0x05f0
-#define IGU_CMD_ATTN_BIT_SET_UPPER			0x05f1
-#define IGU_CMD_ATTN_BIT_CLR_UPPER			0x05f2
+#define IGU_CMD_ATTN_BIT_UPD_UPPER	0x05f0
+#define IGU_CMD_ATTN_BIT_SET_UPPER	0x05f1
+#define IGU_CMD_ATTN_BIT_CLR_UPPER	0x05f2
 
-#define IGU_REG_SISR_MDPC_WMASK_UPPER			0x05f3
-#define IGU_REG_SISR_MDPC_WMASK_LSB_UPPER		0x05f4
-#define IGU_REG_SISR_MDPC_WMASK_MSB_UPPER		0x05f5
-#define IGU_REG_SISR_MDPC_WOMASK_UPPER			0x05f6
+#define IGU_REG_SISR_MDPC_WMASK_UPPER		0x05f3
+#define IGU_REG_SISR_MDPC_WMASK_LSB_UPPER	0x05f4
+#define IGU_REG_SISR_MDPC_WMASK_MSB_UPPER	0x05f5
+#define IGU_REG_SISR_MDPC_WOMASK_UPPER		0x05f6
 
-#define IGU_CMD_PROD_UPD_BASE				0x0600
+#define IGU_CMD_PROD_UPD_BASE			0x0600
 #define IGU_CMD_PROD_UPD_UPPER			(IGU_CMD_PROD_UPD_BASE +\
 						 MAX_TOT_SB_PER_PATH - \
 						 1)
-#define IGU_CMD_PROD_UPD_RESERVED_UPPER			0x07ff
+#define IGU_CMD_PROD_UPD_RESERVED_UPPER		0x07ff
 
 /*****************/
 /* PXP CONSTANTS */
 /*****************/
 
+/* Bars for Blocks */
+#define PXP_BAR_GRC                                         0
+#define PXP_BAR_TSDM                                        0
+#define PXP_BAR_USDM                                        0
+#define PXP_BAR_XSDM                                        0
+#define PXP_BAR_MSDM                                        0
+#define PXP_BAR_YSDM                                        0
+#define PXP_BAR_PSDM                                        0
+#define PXP_BAR_IGU                                         0
+#define PXP_BAR_DQ                                          1
+
 /* PTT and GTT */
-#define PXP_NUM_PF_WINDOWS                                  12
-#define PXP_PER_PF_ENTRY_SIZE                               8
-#define PXP_NUM_GLOBAL_WINDOWS                              243
-#define PXP_GLOBAL_ENTRY_SIZE                               4
-#define PXP_ADMIN_WINDOW_ALLOWED_LENGTH                     4
-#define PXP_PF_WINDOW_ADMIN_START                           0
-#define PXP_PF_WINDOW_ADMIN_LENGTH                          0x1000
+#define PXP_NUM_PF_WINDOWS		12
+#define PXP_PER_PF_ENTRY_SIZE		8
+#define PXP_NUM_GLOBAL_WINDOWS		243
+#define PXP_GLOBAL_ENTRY_SIZE		4
+#define PXP_ADMIN_WINDOW_ALLOWED_LENGTH	4
+#define PXP_PF_WINDOW_ADMIN_START	0
+#define PXP_PF_WINDOW_ADMIN_LENGTH	0x1000
 #define PXP_PF_WINDOW_ADMIN_END		(PXP_PF_WINDOW_ADMIN_START + \
 					 PXP_PF_WINDOW_ADMIN_LENGTH - 1)
-#define PXP_PF_WINDOW_ADMIN_PER_PF_START                    0
+#define PXP_PF_WINDOW_ADMIN_PER_PF_START	0
 #define PXP_PF_WINDOW_ADMIN_PER_PF_LENGTH	(PXP_NUM_PF_WINDOWS * \
 						 PXP_PER_PF_ENTRY_SIZE)
 #define PXP_PF_WINDOW_ADMIN_PER_PF_END	(PXP_PF_WINDOW_ADMIN_PER_PF_START + \
-	 PXP_PF_WINDOW_ADMIN_PER_PF_LENGTH - 1)
-#define PXP_PF_WINDOW_ADMIN_GLOBAL_START                    0x200
+					 PXP_PF_WINDOW_ADMIN_PER_PF_LENGTH - 1)
+#define PXP_PF_WINDOW_ADMIN_GLOBAL_START	0x200
 #define PXP_PF_WINDOW_ADMIN_GLOBAL_LENGTH	(PXP_NUM_GLOBAL_WINDOWS * \
 						 PXP_GLOBAL_ENTRY_SIZE)
-#define PXP_PF_WINDOW_ADMIN_GLOBAL_END                      \
-	(PXP_PF_WINDOW_ADMIN_GLOBAL_START +		    \
-	 PXP_PF_WINDOW_ADMIN_GLOBAL_LENGTH - 1)
-#define PXP_PF_GLOBAL_PRETEND_ADDR                          0x1f0
-#define PXP_PF_ME_OPAQUE_MASK_ADDR                          0xf4
-#define PXP_PF_ME_OPAQUE_ADDR                               0x1f8
-#define PXP_PF_ME_CONCRETE_ADDR                             0x1fc
-
-#define PXP_EXTERNAL_BAR_PF_WINDOW_START                    0x1000
-#define PXP_EXTERNAL_BAR_PF_WINDOW_NUM                      PXP_NUM_PF_WINDOWS
-#define PXP_EXTERNAL_BAR_PF_WINDOW_SINGLE_SIZE              0x1000
-#define PXP_EXTERNAL_BAR_PF_WINDOW_LENGTH                   \
-	(PXP_EXTERNAL_BAR_PF_WINDOW_NUM *		    \
+#define PXP_PF_WINDOW_ADMIN_GLOBAL_END \
+		(PXP_PF_WINDOW_ADMIN_GLOBAL_START + \
+		 PXP_PF_WINDOW_ADMIN_GLOBAL_LENGTH - 1)
+#define PXP_PF_GLOBAL_PRETEND_ADDR	0x1f0
+#define PXP_PF_ME_OPAQUE_MASK_ADDR	0xf4
+#define PXP_PF_ME_OPAQUE_ADDR		0x1f8
+#define PXP_PF_ME_CONCRETE_ADDR		0x1fc
+
+#define PXP_EXTERNAL_BAR_PF_WINDOW_START	0x1000
+#define PXP_EXTERNAL_BAR_PF_WINDOW_NUM		PXP_NUM_PF_WINDOWS
+#define PXP_EXTERNAL_BAR_PF_WINDOW_SINGLE_SIZE	0x1000
+#define PXP_EXTERNAL_BAR_PF_WINDOW_LENGTH \
+	(PXP_EXTERNAL_BAR_PF_WINDOW_NUM * \
 	 PXP_EXTERNAL_BAR_PF_WINDOW_SINGLE_SIZE)
-#define PXP_EXTERNAL_BAR_PF_WINDOW_END                      \
-	(PXP_EXTERNAL_BAR_PF_WINDOW_START +		    \
+#define PXP_EXTERNAL_BAR_PF_WINDOW_END \
+	(PXP_EXTERNAL_BAR_PF_WINDOW_START + \
 	 PXP_EXTERNAL_BAR_PF_WINDOW_LENGTH - 1)
 
-#define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_START                \
+#define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_START \
 	(PXP_EXTERNAL_BAR_PF_WINDOW_END + 1)
 #define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_NUM		PXP_NUM_GLOBAL_WINDOWS
-#define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_SINGLE_SIZE          0x1000
-#define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_LENGTH               \
-	(PXP_EXTERNAL_BAR_GLOBAL_WINDOW_NUM *		    \
+#define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_SINGLE_SIZE	0x1000
+#define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_LENGTH \
+	(PXP_EXTERNAL_BAR_GLOBAL_WINDOW_NUM * \
 	 PXP_EXTERNAL_BAR_GLOBAL_WINDOW_SINGLE_SIZE)
-#define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_END                  \
-	(PXP_EXTERNAL_BAR_GLOBAL_WINDOW_START +		    \
+#define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_END \
+	(PXP_EXTERNAL_BAR_GLOBAL_WINDOW_START + \
 	 PXP_EXTERNAL_BAR_GLOBAL_WINDOW_LENGTH - 1)
 
-#define PXP_ILT_PAGE_SIZE_NUM_BITS_MIN          12
-#define PXP_ILT_BLOCK_FACTOR_MULTIPLIER         1024
+/* PF BAR */
+/*#define PXP_BAR0_START_GRC 0x1000 */
+/*#define PXP_BAR0_GRC_LENGTH 0xBFF000 */
+#define PXP_BAR0_START_GRC                      0x0000
+#define PXP_BAR0_GRC_LENGTH                     0x1C00000
+#define PXP_BAR0_END_GRC                        \
+	(PXP_BAR0_START_GRC + PXP_BAR0_GRC_LENGTH - 1)
+
+#define PXP_BAR0_START_IGU                      0x1C00000
+#define PXP_BAR0_IGU_LENGTH                     0x10000
+#define PXP_BAR0_END_IGU                        \
+	(PXP_BAR0_START_IGU + PXP_BAR0_IGU_LENGTH - 1)
+
+#define PXP_BAR0_START_TSDM                     0x1C80000
+#define PXP_BAR0_SDM_LENGTH                     0x40000
+#define PXP_BAR0_SDM_RESERVED_LENGTH            0x40000
+#define PXP_BAR0_END_TSDM                       \
+	(PXP_BAR0_START_TSDM + PXP_BAR0_SDM_LENGTH - 1)
+
+#define PXP_BAR0_START_MSDM                     0x1D00000
+#define PXP_BAR0_END_MSDM                       \
+	(PXP_BAR0_START_MSDM + PXP_BAR0_SDM_LENGTH - 1)
+
+#define PXP_BAR0_START_USDM                     0x1D80000
+#define PXP_BAR0_END_USDM                       \
+	(PXP_BAR0_START_USDM + PXP_BAR0_SDM_LENGTH - 1)
+
+#define PXP_BAR0_START_XSDM                     0x1E00000
+#define PXP_BAR0_END_XSDM                       \
+	(PXP_BAR0_START_XSDM + PXP_BAR0_SDM_LENGTH - 1)
+
+#define PXP_BAR0_START_YSDM                     0x1E80000
+#define PXP_BAR0_END_YSDM                       \
+	(PXP_BAR0_START_YSDM + PXP_BAR0_SDM_LENGTH - 1)
+
+#define PXP_BAR0_START_PSDM                     0x1F00000
+#define PXP_BAR0_END_PSDM                       \
+	(PXP_BAR0_START_PSDM + PXP_BAR0_SDM_LENGTH - 1)
+
+#define PXP_BAR0_FIRST_INVALID_ADDRESS          \
+	(PXP_BAR0_END_PSDM + 1)
+
+#define PXP_ILT_PAGE_SIZE_NUM_BITS_MIN	12
+#define PXP_ILT_BLOCK_FACTOR_MULTIPLIER	1024
 
 /* ILT Records */
 #define PXP_NUM_ILT_RECORDS_BB 7600
 #define PXP_NUM_ILT_RECORDS_K2 11000
 #define MAX_NUM_ILT_RECORDS MAX(PXP_NUM_ILT_RECORDS_BB, PXP_NUM_ILT_RECORDS_K2)
 
+
+/* Host Interface */
+#define PXP_QUEUES_ZONE_MAX_NUM	320
+
+
+
+
+/*****************/
+/* PRM CONSTANTS */
+/*****************/
+#define PRM_DMA_PAD_BYTES_NUM  2
+/*****************/
+/* SDMs CONSTANTS  */
+/*****************/
+
+
+#define SDM_OP_GEN_TRIG_NONE			0
+#define SDM_OP_GEN_TRIG_WAKE_THREAD		1
+#define SDM_OP_GEN_TRIG_AGG_INT			2
+#define SDM_OP_GEN_TRIG_LOADER			4
+#define SDM_OP_GEN_TRIG_INDICATE_ERROR	6
+#define SDM_OP_GEN_TRIG_RELEASE_THREAD	7
+
+/***********************************************************/
+/* Completion types                                        */
+/***********************************************************/
+
+#define SDM_COMP_TYPE_NONE		0
+#define SDM_COMP_TYPE_WAKE_THREAD	1
+#define SDM_COMP_TYPE_AGG_INT		2
+/* Send direct message to local CM and/or remote CMs. Destinations are defined
+ * by vector in CompParams.
+ */
+#define SDM_COMP_TYPE_CM		3
+#define SDM_COMP_TYPE_LOADER		4
+/* Send direct message to PXP (like "internal write" command) to write to remote
+ * Storm RAM via remote SDM
+ */
+#define SDM_COMP_TYPE_PXP		5
+/* Indicate error per thread */
+#define SDM_COMP_TYPE_INDICATE_ERROR	6
+#define SDM_COMP_TYPE_RELEASE_THREAD	7
+/* Write to local RAM as a completion */
+#define SDM_COMP_TYPE_RAM		8
+
+
 /******************/
 /* PBF CONSTANTS  */
 /******************/
@@ -299,12 +627,43 @@
 /* PRS CONSTANTS */
 /*****************/
 
+#define PRS_GFT_CAM_LINES_NO_MATCH  31
 /* Async data KCQ CQE */
 struct async_data {
-	__le32 cid;
-	__le16 itid;
-	u8 error_code;
-	u8 fw_debug_param;
+	/* Context ID of the connection */
+	__le32	cid;
+	/* Task Id of the task (for error that happened on a a task) */
+	__le16	itid;
+	/* error code - relevant only if the opcode indicates its an error */
+	u8	error_code;
+	/* internal fw debug parameter */
+	u8	fw_debug_param;
+};
+
+/*
+ * Interrupt coalescing TimeSet
+ */
+struct coalescing_timeset {
+	u8 value;
+/* Interrupt coalescing TimeSet (timeout_ticks = TimeSet shl (TimerRes+1)) */
+#define COALESCING_TIMESET_TIMESET_MASK  0x7F
+#define COALESCING_TIMESET_TIMESET_SHIFT 0
+/* Only if this flag is set, timeset will take effect */
+#define COALESCING_TIMESET_VALID_MASK    0x1
+#define COALESCING_TIMESET_VALID_SHIFT   7
+};
+
+struct common_queue_zone {
+	__le16 ring_drv_data_consumer;
+	__le16 reserved;
+};
+
+/*
+ * ETH Rx producers data
+ */
+struct eth_rx_prod_data {
+	__le16 bd_prod /* BD producer. */;
+	__le16 cqe_prod /* CQE producer. */;
 };
 
 struct regpair {
@@ -312,24 +671,38 @@ struct regpair {
 	__le32 hi /* high word for reg-pair */;
 };
 
+/*
+ * Event Ring VF-PF Channel data
+ */
 struct vf_pf_channel_eqe_data {
 	struct regpair msg_addr /* VF-PF message address */;
 };
 
 struct iscsi_eqe_data {
 	__le32 cid /* Context ID of the connection */;
-	__le16 conn_id
 	    /* Task Id of the task (for error that happened on a a task) */;
+	__le16 conn_id;
+/* error code - relevant only if the opcode indicates its an error */
 	u8 error_code;
-	u8 reserved0;
+	u8 error_pdu_opcode_reserved;
+/* The processed PDUs opcode on which happened the error - updated for specific
+ * error codes, by default=0xFF
+ */
+#define ISCSI_EQE_DATA_ERROR_PDU_OPCODE_MASK        0x3F
+#define ISCSI_EQE_DATA_ERROR_PDU_OPCODE_SHIFT       0
+/* Indication for driver is the error_pdu_opcode field has valid value */
+#define ISCSI_EQE_DATA_ERROR_PDU_OPCODE_VALID_MASK  0x1
+#define ISCSI_EQE_DATA_ERROR_PDU_OPCODE_VALID_SHIFT 6
+#define ISCSI_EQE_DATA_RESERVED0_MASK               0x1
+#define ISCSI_EQE_DATA_RESERVED0_SHIFT              7
 };
 
 /*
  * Event Ring malicious VF data
  */
 struct malicious_vf_eqe_data {
-	u8 vf_id /* Malicious VF ID */; /* WARNING:CAMELCASE */
-	u8 err_id /* Malicious VF error */;
+	u8 vfId /* Malicious VF ID */;
+	u8 errId /* Malicious VF error */;
 	__le16 reserved[3];
 };
 
@@ -337,41 +710,46 @@ struct malicious_vf_eqe_data {
  * Event Ring initial cleanup data
  */
 struct initial_cleanup_eqe_data {
-	u8 vf_id /* VF ID */; /* WARNING:CAMELCASE */
+	u8 vfId /* VF ID */;
 	u8 reserved[7];
 };
 
-
+/*
+ * Event Data Union
+ */
 union event_ring_data {
 	u8 bytes[8] /* Byte Array */;
 	struct vf_pf_channel_eqe_data vf_pf_channel /* VF-PF Channel data */;
 	struct iscsi_eqe_data iscsi_info /* Dedicated fields to iscsi data */;
-	struct regpair roce_handle /* WARNING:CAMELCASE */
 	    /* Dedicated field for RoCE affiliated asynchronous error */;
+	struct regpair roceHandle;
 	struct malicious_vf_eqe_data malicious_vf /* Malicious VF data */;
 	struct initial_cleanup_eqe_data vf_init_cleanup
 	    /* VF Initial Cleanup data */;
+/* Host handle for the Async Completions */
+	struct regpair iwarp_handle;
 };
 /* Event Ring Entry */
 struct event_ring_entry {
-	u8			protocol_id;
-	u8			opcode;
-	__le16			reserved0;
-	__le16			echo;
-	u8			fw_return_code;
+	u8 protocol_id /* Event Protocol ID */;
+	u8 opcode /* Event Opcode */;
+	__le16 reserved0 /* Reserved */;
+	__le16 echo /* Echo value from ramrod data on the host */;
+	u8 fw_return_code /* FW return code for SP ramrods */;
 	u8 flags;
+/* 0: synchronous EQE - a completion of SP message. 1: asynchronous EQE */
 #define EVENT_RING_ENTRY_ASYNC_MASK      0x1
 #define EVENT_RING_ENTRY_ASYNC_SHIFT     0
 #define EVENT_RING_ENTRY_RESERVED1_MASK  0x7F
 #define EVENT_RING_ENTRY_RESERVED1_SHIFT 1
-	union event_ring_data data;
+	union event_ring_data	data;
 };
 
 /* Multi function mode */
 enum mf_mode {
-	SF,
-	MF_OVLAN,
-	MF_NPAR,
+	ERROR_MODE /* Unsupported mode */,
+	MF_OVLAN /* Multi function based on outer VLAN */,
+	MF_NPAR /* Multi function based on MAC address (NIC partitioning) */,
 	MAX_MF_MODE
 };
 
@@ -390,35 +768,59 @@ enum protocol_type {
 	MAX_PROTOCOL_TYPE
 };
 
+/*
+ * Ustorm Queue Zone
+ */
+struct ustorm_eth_queue_zone {
+/* Rx interrupt coalescing TimeSet */
+	struct coalescing_timeset int_coalescing_timeset;
+	u8 reserved[3];
+};
+
+
+struct ustorm_queue_zone {
+	struct ustorm_eth_queue_zone eth;
+	struct common_queue_zone common;
+};
+
 /* status block structure */
 struct cau_pi_entry {
-	u32 prod;
+	__le32 prod;
+/* A per protocol indexPROD value. */
 #define CAU_PI_ENTRY_PROD_VAL_MASK    0xFFFF
 #define CAU_PI_ENTRY_PROD_VAL_SHIFT   0
+/* This value determines the TimeSet that the PI is associated with */
 #define CAU_PI_ENTRY_PI_TIMESET_MASK  0x7F
 #define CAU_PI_ENTRY_PI_TIMESET_SHIFT 16
+/* Select the FSM within the SB */
 #define CAU_PI_ENTRY_FSM_SEL_MASK     0x1
 #define CAU_PI_ENTRY_FSM_SEL_SHIFT    23
+/* Select the FSM within the SB */
 #define CAU_PI_ENTRY_RESERVED_MASK    0xFF
 #define CAU_PI_ENTRY_RESERVED_SHIFT   24
 };
 
 /* status block structure */
 struct cau_sb_entry {
-	u32 data;
+	__le32 data;
+/* The SB PROD index which is sent to the IGU. */
 #define CAU_SB_ENTRY_SB_PROD_MASK      0xFFFFFF
 #define CAU_SB_ENTRY_SB_PROD_SHIFT     0
-#define CAU_SB_ENTRY_STATE0_MASK       0xF
+#define CAU_SB_ENTRY_STATE0_MASK       0xF /* RX state */
 #define CAU_SB_ENTRY_STATE0_SHIFT      24
-#define CAU_SB_ENTRY_STATE1_MASK       0xF
+#define CAU_SB_ENTRY_STATE1_MASK       0xF /* TX state */
 #define CAU_SB_ENTRY_STATE1_SHIFT      28
-	u32 params;
+	__le32 params;
+/* Indicates the RX TimeSet that this SB is associated with. */
 #define CAU_SB_ENTRY_SB_TIMESET0_MASK  0x7F
 #define CAU_SB_ENTRY_SB_TIMESET0_SHIFT 0
+/* Indicates the TX TimeSet that this SB is associated with. */
 #define CAU_SB_ENTRY_SB_TIMESET1_MASK  0x7F
 #define CAU_SB_ENTRY_SB_TIMESET1_SHIFT 7
+/* This value will determine the RX FSM timer resolution in ticks */
 #define CAU_SB_ENTRY_TIMER_RES0_MASK   0x3
 #define CAU_SB_ENTRY_TIMER_RES0_SHIFT  14
+/* This value will determine the TX FSM timer resolution in ticks */
 #define CAU_SB_ENTRY_TIMER_RES1_MASK   0x3
 #define CAU_SB_ENTRY_TIMER_RES1_SHIFT  16
 #define CAU_SB_ENTRY_VF_NUMBER_MASK    0xFF
@@ -427,6 +829,9 @@ struct cau_sb_entry {
 #define CAU_SB_ENTRY_VF_VALID_SHIFT    26
 #define CAU_SB_ENTRY_PF_NUMBER_MASK    0xF
 #define CAU_SB_ENTRY_PF_NUMBER_SHIFT   27
+/* If set then indicates that the TPH STAG is equal to the SB number. Otherwise
+ * the STAG will be equal to all ones.
+ */
 #define CAU_SB_ENTRY_TPH_MASK          0x1
 #define CAU_SB_ENTRY_TPH_SHIFT         31
 };
@@ -434,125 +839,317 @@ struct cau_sb_entry {
 /* core doorbell data */
 struct core_db_data {
 	u8 params;
+/* destination of doorbell (use enum db_dest) */
 #define CORE_DB_DATA_DEST_MASK         0x3
 #define CORE_DB_DATA_DEST_SHIFT        0
+/* aggregative command to CM (use enum db_agg_cmd_sel) */
 #define CORE_DB_DATA_AGG_CMD_MASK      0x3
 #define CORE_DB_DATA_AGG_CMD_SHIFT     2
-#define CORE_DB_DATA_BYPASS_EN_MASK    0x1
+#define CORE_DB_DATA_BYPASS_EN_MASK    0x1 /* enable QM bypass */
 #define CORE_DB_DATA_BYPASS_EN_SHIFT   4
 #define CORE_DB_DATA_RESERVED_MASK     0x1
 #define CORE_DB_DATA_RESERVED_SHIFT    5
+/* aggregative value selection */
 #define CORE_DB_DATA_AGG_VAL_SEL_MASK  0x3
 #define CORE_DB_DATA_AGG_VAL_SEL_SHIFT 6
-	u8 agg_flags;
-	__le16 spq_prod;
+/* bit for every DQ counter flags in CM context that DQ can increment */
+	u8	agg_flags;
+	__le16	spq_prod;
 };
 
 /* Enum of doorbell aggregative command selection */
 enum db_agg_cmd_sel {
-	DB_AGG_CMD_NOP,
-	DB_AGG_CMD_SET,
-	DB_AGG_CMD_ADD,
-	DB_AGG_CMD_MAX,
+	DB_AGG_CMD_NOP /* No operation */,
+	DB_AGG_CMD_SET /* Set the value */,
+	DB_AGG_CMD_ADD /* Add the value */,
+	DB_AGG_CMD_MAX /* Set max of current and new value */,
 	MAX_DB_AGG_CMD_SEL
 };
 
 /* Enum of doorbell destination */
 enum db_dest {
-	DB_DEST_XCM,
-	DB_DEST_UCM,
-	DB_DEST_TCM,
+	DB_DEST_XCM /* TX doorbell to XCM */,
+	DB_DEST_UCM /* RX doorbell to UCM */,
+	DB_DEST_TCM /* RX doorbell to TCM */,
 	DB_NUM_DESTINATIONS,
 	MAX_DB_DEST
 };
 
+
+/*
+ * Enum of doorbell DPM types
+ */
+enum db_dpm_type {
+	DPM_LEGACY /* Legacy DPM- to Xstorm RAM */,
+	DPM_ROCE /* RoCE DPM- to NIG */,
+/* L2 DPM inline- to PBF, with packet data on doorbell */
+	DPM_L2_INLINE,
+	DPM_L2_BD /* L2 DPM with BD- to PBF, with TX BD data on doorbell */,
+	MAX_DB_DPM_TYPE
+};
+
+/*
+ * Structure for doorbell data, in L2 DPM mode, for the first doorbell in a DPM
+ * burst
+ */
+struct db_l2_dpm_data {
+	__le16 icid /* internal CID */;
+	__le16 bd_prod /* bd producer value to update */;
+	__le32 params;
+/* Size in QWORD-s of the DPM burst */
+#define DB_L2_DPM_DATA_SIZE_MASK       0x3F
+#define DB_L2_DPM_DATA_SIZE_SHIFT      0
+/* Type of DPM transaction (DPM_L2_INLINE or DPM_L2_BD) (use enum db_dpm_type)
+ */
+#define DB_L2_DPM_DATA_DPM_TYPE_MASK   0x3
+#define DB_L2_DPM_DATA_DPM_TYPE_SHIFT  6
+#define DB_L2_DPM_DATA_NUM_BDS_MASK    0xFF /* number of BD-s */
+#define DB_L2_DPM_DATA_NUM_BDS_SHIFT   8
+/* size of the packet to be transmitted in bytes */
+#define DB_L2_DPM_DATA_PKT_SIZE_MASK   0x7FF
+#define DB_L2_DPM_DATA_PKT_SIZE_SHIFT  16
+#define DB_L2_DPM_DATA_RESERVED0_MASK  0x1
+#define DB_L2_DPM_DATA_RESERVED0_SHIFT 27
+/* In DPM_L2_BD mode: the number of SGE-s */
+#define DB_L2_DPM_DATA_SGE_NUM_MASK    0x7
+#define DB_L2_DPM_DATA_SGE_NUM_SHIFT   28
+#define DB_L2_DPM_DATA_RESERVED1_MASK  0x1
+#define DB_L2_DPM_DATA_RESERVED1_SHIFT 31
+};
+
+/*
+ * Structure for SGE in a DPM doorbell of type DPM_L2_BD
+ */
+struct db_l2_dpm_sge {
+	struct regpair addr /* Single continuous buffer */;
+	__le16 nbytes /* Number of bytes in this BD. */;
+	__le16 bitfields;
+/* The TPH STAG index value */
+#define DB_L2_DPM_SGE_TPH_ST_INDEX_MASK  0x1FF
+#define DB_L2_DPM_SGE_TPH_ST_INDEX_SHIFT 0
+#define DB_L2_DPM_SGE_RESERVED0_MASK     0x3
+#define DB_L2_DPM_SGE_RESERVED0_SHIFT    9
+/* Indicate if ST hint is requested or not */
+#define DB_L2_DPM_SGE_ST_VALID_MASK      0x1
+#define DB_L2_DPM_SGE_ST_VALID_SHIFT     11
+#define DB_L2_DPM_SGE_RESERVED1_MASK     0xF
+#define DB_L2_DPM_SGE_RESERVED1_SHIFT    12
+	__le32 reserved2;
+};
+
 /* Structure for doorbell address, in legacy mode */
 struct db_legacy_addr {
 	__le32 addr;
 #define DB_LEGACY_ADDR_RESERVED0_MASK  0x3
 #define DB_LEGACY_ADDR_RESERVED0_SHIFT 0
+/* doorbell extraction mode specifier- 0 if not used */
 #define DB_LEGACY_ADDR_DEMS_MASK       0x7
 #define DB_LEGACY_ADDR_DEMS_SHIFT      2
-#define DB_LEGACY_ADDR_ICID_MASK       0x7FFFFFF
+#define DB_LEGACY_ADDR_ICID_MASK       0x7FFFFFF /* internal CID */
 #define DB_LEGACY_ADDR_ICID_SHIFT      5
 };
 
+/*
+ * Structure for doorbell address, in PWM mode
+ */
+struct db_pwm_addr {
+	__le32 addr;
+#define DB_PWM_ADDR_RESERVED0_MASK  0x7
+#define DB_PWM_ADDR_RESERVED0_SHIFT 0
+/* Offset in PWM address space */
+#define DB_PWM_ADDR_OFFSET_MASK     0x7F
+#define DB_PWM_ADDR_OFFSET_SHIFT    3
+#define DB_PWM_ADDR_WID_MASK        0x3 /* Window ID */
+#define DB_PWM_ADDR_WID_SHIFT       10
+#define DB_PWM_ADDR_DPI_MASK        0xFFFF /* Doorbell page ID */
+#define DB_PWM_ADDR_DPI_SHIFT       12
+#define DB_PWM_ADDR_RESERVED1_MASK  0xF
+#define DB_PWM_ADDR_RESERVED1_SHIFT 28
+};
+
+/*
+ * Parameters to RoCE firmware, passed in EDPM doorbell
+ */
+struct db_roce_dpm_params {
+	__le32 params;
+/* Size in QWORD-s of the DPM burst */
+#define DB_ROCE_DPM_PARAMS_SIZE_MASK            0x3F
+#define DB_ROCE_DPM_PARAMS_SIZE_SHIFT           0
+/* Type of DPM transacation (DPM_ROCE) (use enum db_dpm_type) */
+#define DB_ROCE_DPM_PARAMS_DPM_TYPE_MASK        0x3
+#define DB_ROCE_DPM_PARAMS_DPM_TYPE_SHIFT       6
+/* opcode for ROCE operation */
+#define DB_ROCE_DPM_PARAMS_OPCODE_MASK          0xFF
+#define DB_ROCE_DPM_PARAMS_OPCODE_SHIFT         8
+/* the size of the WQE payload in bytes */
+#define DB_ROCE_DPM_PARAMS_WQE_SIZE_MASK        0x7FF
+#define DB_ROCE_DPM_PARAMS_WQE_SIZE_SHIFT       16
+#define DB_ROCE_DPM_PARAMS_RESERVED0_MASK       0x1
+#define DB_ROCE_DPM_PARAMS_RESERVED0_SHIFT      27
+/* RoCE completion flag */
+#define DB_ROCE_DPM_PARAMS_COMPLETION_FLG_MASK  0x1
+#define DB_ROCE_DPM_PARAMS_COMPLETION_FLG_SHIFT 28
+#define DB_ROCE_DPM_PARAMS_S_FLG_MASK           0x1 /* RoCE S flag */
+#define DB_ROCE_DPM_PARAMS_S_FLG_SHIFT          29
+#define DB_ROCE_DPM_PARAMS_RESERVED1_MASK       0x3
+#define DB_ROCE_DPM_PARAMS_RESERVED1_SHIFT      30
+};
+
+/*
+ * Structure for doorbell data, in ROCE DPM mode, for the first doorbell in a
+ * DPM burst
+ */
+struct db_roce_dpm_data {
+	__le16 icid /* internal CID */;
+	__le16 prod_val /* aggregated value to update */;
+/* parameters passed to RoCE firmware */
+	struct db_roce_dpm_params params;
+};
+
 /* Igu interrupt command */
 enum igu_int_cmd {
-	IGU_INT_ENABLE = 0,
+	IGU_INT_ENABLE	= 0,
 	IGU_INT_DISABLE = 1,
-	IGU_INT_NOP = 2,
-	IGU_INT_NOP2 = 3,
+	IGU_INT_NOP	= 2,
+	IGU_INT_NOP2	= 3,
 	MAX_IGU_INT_CMD
 };
 
 /* IGU producer or consumer update command */
 struct igu_prod_cons_update {
-	u32 sb_id_and_flags;
+	__le32 sb_id_and_flags;
 #define IGU_PROD_CONS_UPDATE_SB_INDEX_MASK        0xFFFFFF
 #define IGU_PROD_CONS_UPDATE_SB_INDEX_SHIFT       0
 #define IGU_PROD_CONS_UPDATE_UPDATE_FLAG_MASK     0x1
 #define IGU_PROD_CONS_UPDATE_UPDATE_FLAG_SHIFT    24
+/* interrupt enable/disable/nop (use enum igu_int_cmd) */
 #define IGU_PROD_CONS_UPDATE_ENABLE_INT_MASK      0x3
 #define IGU_PROD_CONS_UPDATE_ENABLE_INT_SHIFT     25
+/*  (use enum igu_seg_access) */
 #define IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_MASK  0x1
 #define IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_SHIFT 27
 #define IGU_PROD_CONS_UPDATE_TIMER_MASK_MASK      0x1
 #define IGU_PROD_CONS_UPDATE_TIMER_MASK_SHIFT     28
 #define IGU_PROD_CONS_UPDATE_RESERVED0_MASK       0x3
 #define IGU_PROD_CONS_UPDATE_RESERVED0_SHIFT      29
+/* must always be set cleared (use enum command_type_bit) */
 #define IGU_PROD_CONS_UPDATE_COMMAND_TYPE_MASK    0x1
 #define IGU_PROD_CONS_UPDATE_COMMAND_TYPE_SHIFT   31
-	u32 reserved1;
+	__le32 reserved1;
 };
 
 /* Igu segments access for default status block only */
 enum igu_seg_access {
-	IGU_SEG_ACCESS_REG = 0,
-	IGU_SEG_ACCESS_ATTN = 1,
+	IGU_SEG_ACCESS_REG	= 0,
+	IGU_SEG_ACCESS_ATTN	= 1,
 	MAX_IGU_SEG_ACCESS
 };
 
+
+/*
+ * Enumeration for L3 type field of parsing_and_err_flags_union. L3Type:
+ * 0 - unknown (not ip) ,1 - Ipv4, 2 - Ipv6 (this field can be filled according
+ * to the last-ethertype)
+ */
+enum l3_type {
+	e_l3Type_unknown,
+	e_l3Type_ipv4,
+	e_l3Type_ipv6,
+	MAX_L3_TYPE
+};
+
+
+/*
+ * Enumeration for l4Protocol field of parsing_and_err_flags_union. L4-protocol
+ * 0 - none, 1 - TCP, 2- UDP. if the packet is IPv4 fragment, and its not the
+ * first fragment, the protocol-type should be set to none.
+ */
+enum l4_protocol {
+	e_l4Protocol_none,
+	e_l4Protocol_tcp,
+	e_l4Protocol_udp,
+	MAX_L4_PROTOCOL
+};
+
+
+/*
+ * Parsing and error flags field.
+ */
 struct parsing_and_err_flags {
 	__le16 flags;
+/* L3Type: 0 - unknown (not ip) ,1 - Ipv4, 2 - Ipv6 (this field can be filled
+ * according to the last-ethertype) (use enum l3_type)
+ */
 #define PARSING_AND_ERR_FLAGS_L3TYPE_MASK                      0x3
 #define PARSING_AND_ERR_FLAGS_L3TYPE_SHIFT                     0
+/* L4-protocol 0 - none, 1 - TCP, 2- UDP. if the packet is IPv4 fragment, and
+ * its not the first fragment, the protocol-type should be set to none.
+ * (use enum l4_protocol)
+ */
 #define PARSING_AND_ERR_FLAGS_L4PROTOCOL_MASK                  0x3
 #define PARSING_AND_ERR_FLAGS_L4PROTOCOL_SHIFT                 2
+/* Set if the packet is IPv4 fragment. */
 #define PARSING_AND_ERR_FLAGS_IPV4FRAG_MASK                    0x1
 #define PARSING_AND_ERR_FLAGS_IPV4FRAG_SHIFT                   4
+/* Set if VLAN tag exists. Invalid if tunnel type are IP GRE or IP GENEVE. */
 #define PARSING_AND_ERR_FLAGS_TAG8021QEXIST_MASK               0x1
 #define PARSING_AND_ERR_FLAGS_TAG8021QEXIST_SHIFT              5
+/* Set if L4 checksum was calculated. */
 #define PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_MASK        0x1
 #define PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_SHIFT       6
+/* Set for PTP packet. */
 #define PARSING_AND_ERR_FLAGS_TIMESYNCPKT_MASK                 0x1
 #define PARSING_AND_ERR_FLAGS_TIMESYNCPKT_SHIFT                7
+/* Set if PTP timestamp recorded. */
 #define PARSING_AND_ERR_FLAGS_TIMESTAMPRECORDED_MASK           0x1
 #define PARSING_AND_ERR_FLAGS_TIMESTAMPRECORDED_SHIFT          8
+/* Set if either version-mismatch or hdr-len-error or ipv4-cksm is set or ipv6
+ * ver mismatch
+ */
 #define PARSING_AND_ERR_FLAGS_IPHDRERROR_MASK                  0x1
 #define PARSING_AND_ERR_FLAGS_IPHDRERROR_SHIFT                 9
+/* Set if L4 checksum validation failed. Valid only if L4 checksum was
+ * calculated.
+ */
 #define PARSING_AND_ERR_FLAGS_L4CHKSMERROR_MASK                0x1
 #define PARSING_AND_ERR_FLAGS_L4CHKSMERROR_SHIFT               10
+/* Set if GRE/VXLAN/GENEVE tunnel detected. */
 #define PARSING_AND_ERR_FLAGS_TUNNELEXIST_MASK                 0x1
 #define PARSING_AND_ERR_FLAGS_TUNNELEXIST_SHIFT                11
+/* Set if VLAN tag exists in tunnel header. */
 #define PARSING_AND_ERR_FLAGS_TUNNEL8021QTAGEXIST_MASK         0x1
 #define PARSING_AND_ERR_FLAGS_TUNNEL8021QTAGEXIST_SHIFT        12
+/* Set if either tunnel-ipv4-version-mismatch or tunnel-ipv4-hdr-len-error or
+ * tunnel-ipv4-cksm is set or tunneling ipv6 ver mismatch
+ */
 #define PARSING_AND_ERR_FLAGS_TUNNELIPHDRERROR_MASK            0x1
 #define PARSING_AND_ERR_FLAGS_TUNNELIPHDRERROR_SHIFT           13
+/* Set if GRE or VXLAN/GENEVE UDP checksum was calculated. */
 #define PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMWASCALCULATED_MASK  0x1
 #define PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMWASCALCULATED_SHIFT 14
+/* Set if tunnel L4 checksum validation failed. Valid only if tunnel L4 checksum
+ * was calculated.
+ */
 #define PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMERROR_MASK          0x1
 #define PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMERROR_SHIFT         15
 };
 
+
+/*
+ * Pb context
+ */
+struct pb_context {
+	__le32 crc[4];
+};
+
 /* Concrete Function ID. */
 struct pxp_concrete_fid {
 	__le16 fid;
-#define PXP_CONCRETE_FID_PFID_MASK     0xF
+#define PXP_CONCRETE_FID_PFID_MASK     0xF /* Parent PFID */
 #define PXP_CONCRETE_FID_PFID_SHIFT    0
-#define PXP_CONCRETE_FID_PORT_MASK     0x3
+#define PXP_CONCRETE_FID_PORT_MASK     0x3 /* port number */
 #define PXP_CONCRETE_FID_PORT_SHIFT    4
-#define PXP_CONCRETE_FID_PATH_MASK     0x1
+#define PXP_CONCRETE_FID_PATH_MASK     0x1 /* path number */
 #define PXP_CONCRETE_FID_PATH_SHIFT    6
 #define PXP_CONCRETE_FID_VFVALID_MASK  0x1
 #define PXP_CONCRETE_FID_VFVALID_SHIFT 7
@@ -574,13 +1171,13 @@ struct pxp_pretend_concrete_fid {
 
 union pxp_pretend_fid {
 	struct pxp_pretend_concrete_fid concrete_fid;
-	__le16 opaque_fid;
+	__le16				opaque_fid;
 };
 
 /* Pxp Pretend Command Register. */
 struct pxp_pretend_cmd {
-	union pxp_pretend_fid fid;
-	__le16 control;
+	union pxp_pretend_fid	fid;
+	__le16			control;
 #define PXP_PRETEND_CMD_PATH_MASK              0x1
 #define PXP_PRETEND_CMD_PATH_SHIFT             0
 #define PXP_PRETEND_CMD_USE_PORT_MASK          0x1
@@ -603,30 +1200,127 @@ struct pxp_pretend_cmd {
 
 /* PTT Record in PXP Admin Window. */
 struct pxp_ptt_entry {
-	__le32 offset;
+	__le32			offset;
 #define PXP_PTT_ENTRY_OFFSET_MASK     0x7FFFFF
 #define PXP_PTT_ENTRY_OFFSET_SHIFT    0
 #define PXP_PTT_ENTRY_RESERVED0_MASK  0x1FF
 #define PXP_PTT_ENTRY_RESERVED0_SHIFT 23
-	struct pxp_pretend_cmd pretend;
+	struct pxp_pretend_cmd	pretend;
+};
+
+
+/*
+ * VF Zone A Permission Register.
+ */
+struct pxp_vf_zone_a_permission {
+	__le32 control;
+#define PXP_VF_ZONE_A_PERMISSION_VFID_MASK       0xFF
+#define PXP_VF_ZONE_A_PERMISSION_VFID_SHIFT      0
+#define PXP_VF_ZONE_A_PERMISSION_VALID_MASK      0x1
+#define PXP_VF_ZONE_A_PERMISSION_VALID_SHIFT     8
+#define PXP_VF_ZONE_A_PERMISSION_RESERVED0_MASK  0x7F
+#define PXP_VF_ZONE_A_PERMISSION_RESERVED0_SHIFT 9
+#define PXP_VF_ZONE_A_PERMISSION_RESERVED1_MASK  0xFFFF
+#define PXP_VF_ZONE_A_PERMISSION_RESERVED1_SHIFT 16
+};
+
+
+/*
+ * Rdif context
+ */
+struct rdif_task_context {
+	__le32 initialRefTag;
+	__le16 appTagValue;
+	__le16 appTagMask;
+	u8 flags0;
+#define RDIF_TASK_CONTEXT_IGNOREAPPTAG_MASK            0x1
+#define RDIF_TASK_CONTEXT_IGNOREAPPTAG_SHIFT           0
+#define RDIF_TASK_CONTEXT_INITIALREFTAGVALID_MASK      0x1
+#define RDIF_TASK_CONTEXT_INITIALREFTAGVALID_SHIFT     1
+/* 0 = IP checksum, 1 = CRC */
+#define RDIF_TASK_CONTEXT_HOSTGUARDTYPE_MASK           0x1
+#define RDIF_TASK_CONTEXT_HOSTGUARDTYPE_SHIFT          2
+#define RDIF_TASK_CONTEXT_SETERRORWITHEOP_MASK         0x1
+#define RDIF_TASK_CONTEXT_SETERRORWITHEOP_SHIFT        3
+/* 1/2/3 - Protection Type */
+#define RDIF_TASK_CONTEXT_PROTECTIONTYPE_MASK          0x3
+#define RDIF_TASK_CONTEXT_PROTECTIONTYPE_SHIFT         4
+/* 0=0x0000, 1=0xffff */
+#define RDIF_TASK_CONTEXT_CRC_SEED_MASK                0x1
+#define RDIF_TASK_CONTEXT_CRC_SEED_SHIFT               6
+/* Keep reference tag constant */
+#define RDIF_TASK_CONTEXT_KEEPREFTAGCONST_MASK         0x1
+#define RDIF_TASK_CONTEXT_KEEPREFTAGCONST_SHIFT        7
+	u8 partialDifData[7];
+	__le16 partialCrcValue;
+	__le16 partialChecksumValue;
+	__le32 offsetInIO;
+	__le16 flags1;
+#define RDIF_TASK_CONTEXT_VALIDATEGUARD_MASK           0x1
+#define RDIF_TASK_CONTEXT_VALIDATEGUARD_SHIFT          0
+#define RDIF_TASK_CONTEXT_VALIDATEAPPTAG_MASK          0x1
+#define RDIF_TASK_CONTEXT_VALIDATEAPPTAG_SHIFT         1
+#define RDIF_TASK_CONTEXT_VALIDATEREFTAG_MASK          0x1
+#define RDIF_TASK_CONTEXT_VALIDATEREFTAG_SHIFT         2
+#define RDIF_TASK_CONTEXT_FORWARDGUARD_MASK            0x1
+#define RDIF_TASK_CONTEXT_FORWARDGUARD_SHIFT           3
+#define RDIF_TASK_CONTEXT_FORWARDAPPTAG_MASK           0x1
+#define RDIF_TASK_CONTEXT_FORWARDAPPTAG_SHIFT          4
+#define RDIF_TASK_CONTEXT_FORWARDREFTAG_MASK           0x1
+#define RDIF_TASK_CONTEXT_FORWARDREFTAG_SHIFT          5
+/* 0=512B, 1=1KB, 2=2KB, 3=4KB, 4=8KB */
+#define RDIF_TASK_CONTEXT_INTERVALSIZE_MASK            0x7
+#define RDIF_TASK_CONTEXT_INTERVALSIZE_SHIFT           6
+/* 0=None, 1=DIF, 2=DIX */
+#define RDIF_TASK_CONTEXT_HOSTINTERFACE_MASK           0x3
+#define RDIF_TASK_CONTEXT_HOSTINTERFACE_SHIFT          9
+/* DIF tag right at the beginning of DIF interval */
+#define RDIF_TASK_CONTEXT_DIFBEFOREDATA_MASK           0x1
+#define RDIF_TASK_CONTEXT_DIFBEFOREDATA_SHIFT          11
+#define RDIF_TASK_CONTEXT_RESERVED0_MASK               0x1
+#define RDIF_TASK_CONTEXT_RESERVED0_SHIFT              12
+/* 0=None, 1=DIF */
+#define RDIF_TASK_CONTEXT_NETWORKINTERFACE_MASK        0x1
+#define RDIF_TASK_CONTEXT_NETWORKINTERFACE_SHIFT       13
+/* Forward application tag with mask */
+#define RDIF_TASK_CONTEXT_FORWARDAPPTAGWITHMASK_MASK   0x1
+#define RDIF_TASK_CONTEXT_FORWARDAPPTAGWITHMASK_SHIFT  14
+/* Forward reference tag with mask */
+#define RDIF_TASK_CONTEXT_FORWARDREFTAGWITHMASK_MASK   0x1
+#define RDIF_TASK_CONTEXT_FORWARDREFTAGWITHMASK_SHIFT  15
+	__le16 state;
+#define RDIF_TASK_CONTEXT_RECEIVEDDIFBYTESLEFT_MASK    0xF
+#define RDIF_TASK_CONTEXT_RECEIVEDDIFBYTESLEFT_SHIFT   0
+#define RDIF_TASK_CONTEXT_TRANSMITEDDIFBYTESLEFT_MASK  0xF
+#define RDIF_TASK_CONTEXT_TRANSMITEDDIFBYTESLEFT_SHIFT 4
+#define RDIF_TASK_CONTEXT_ERRORINIO_MASK               0x1
+#define RDIF_TASK_CONTEXT_ERRORINIO_SHIFT              8
+#define RDIF_TASK_CONTEXT_CHECKSUMOVERFLOW_MASK        0x1
+#define RDIF_TASK_CONTEXT_CHECKSUMOVERFLOW_SHIFT       9
+/* mask for refernce tag handling */
+#define RDIF_TASK_CONTEXT_REFTAGMASK_MASK              0xF
+#define RDIF_TASK_CONTEXT_REFTAGMASK_SHIFT             10
+#define RDIF_TASK_CONTEXT_RESERVED1_MASK               0x3
+#define RDIF_TASK_CONTEXT_RESERVED1_SHIFT              14
+	__le32 reserved2;
 };
 
 /* RSS hash type */
 enum rss_hash_type {
-	RSS_HASH_TYPE_DEFAULT = 0,
-	RSS_HASH_TYPE_IPV4 = 1,
-	RSS_HASH_TYPE_TCP_IPV4 = 2,
-	RSS_HASH_TYPE_IPV6 = 3,
-	RSS_HASH_TYPE_TCP_IPV6 = 4,
-	RSS_HASH_TYPE_UDP_IPV4 = 5,
-	RSS_HASH_TYPE_UDP_IPV6 = 6,
+	RSS_HASH_TYPE_DEFAULT	= 0,
+	RSS_HASH_TYPE_IPV4	= 1,
+	RSS_HASH_TYPE_TCP_IPV4	= 2,
+	RSS_HASH_TYPE_IPV6	= 3,
+	RSS_HASH_TYPE_TCP_IPV6	= 4,
+	RSS_HASH_TYPE_UDP_IPV4	= 5,
+	RSS_HASH_TYPE_UDP_IPV6	= 6,
 	MAX_RSS_HASH_TYPE
 };
 
 /* status block structure */
 struct status_block {
-	__le16 pi_array[PIS_PER_SB];
-	__le32 sb_num;
+	__le16	pi_array[PIS_PER_SB];
+	__le32	sb_num;
 #define STATUS_BLOCK_SB_NUM_MASK      0x1FF
 #define STATUS_BLOCK_SB_NUM_SHIFT     0
 #define STATUS_BLOCK_ZERO_PAD_MASK    0x7F
@@ -640,20 +1334,6 @@ struct status_block {
 #define STATUS_BLOCK_ZERO_PAD3_SHIFT  24
 };
 
-/* @DPDK */
-#define X_FINAL_CLEANUP_AGG_INT  1
-#define SDM_COMP_TYPE_AGG_INT 2
-#define MAX_NUM_LL2_RX_QUEUES 32
-#define QM_PQ_ELEMENT_SIZE 4
-#define PXP_VF_BAR0_START_IGU 0
-#define EAGLE_ENG1_WORKAROUND_NIG_FLOWCTRL_MODE 3
-
-#define TSTORM_QZONE_SIZE 8
-#define MSTORM_QZONE_SIZE 16
-#define USTORM_QZONE_SIZE 8
-#define XSTORM_QZONE_SIZE 0
-#define YSTORM_QZONE_SIZE 8
-#define PSTORM_QZONE_SIZE 0
 
 /* VF BAR */
 #define PXP_VF_BAR0 0
@@ -708,7 +1388,165 @@ struct status_block {
 
 #define PXP_VF_BAR0_GRC_WINDOW_LENGTH   32
 
-#define PXP_ILT_PAGE_SIZE_NUM_BITS_MIN  12
-#define PXP_ILT_BLOCK_FACTOR_MULTIPLIER 1024
+/*
+ * Tdif context
+ */
+struct tdif_task_context {
+	__le32 initialRefTag;
+	__le16 appTagValue;
+	__le16 appTagMask;
+	__le16 partialCrcValueB;
+	__le16 partialChecksumValueB;
+	__le16 stateB;
+#define TDIF_TASK_CONTEXT_RECEIVEDDIFBYTESLEFTB_MASK    0xF
+#define TDIF_TASK_CONTEXT_RECEIVEDDIFBYTESLEFTB_SHIFT   0
+#define TDIF_TASK_CONTEXT_TRANSMITEDDIFBYTESLEFTB_MASK  0xF
+#define TDIF_TASK_CONTEXT_TRANSMITEDDIFBYTESLEFTB_SHIFT 4
+#define TDIF_TASK_CONTEXT_ERRORINIOB_MASK               0x1
+#define TDIF_TASK_CONTEXT_ERRORINIOB_SHIFT              8
+#define TDIF_TASK_CONTEXT_CHECKSUMOVERFLOW_MASK         0x1
+#define TDIF_TASK_CONTEXT_CHECKSUMOVERFLOW_SHIFT        9
+#define TDIF_TASK_CONTEXT_RESERVED0_MASK                0x3F
+#define TDIF_TASK_CONTEXT_RESERVED0_SHIFT               10
+	u8 reserved1;
+	u8 flags0;
+#define TDIF_TASK_CONTEXT_IGNOREAPPTAG_MASK             0x1
+#define TDIF_TASK_CONTEXT_IGNOREAPPTAG_SHIFT            0
+#define TDIF_TASK_CONTEXT_INITIALREFTAGVALID_MASK       0x1
+#define TDIF_TASK_CONTEXT_INITIALREFTAGVALID_SHIFT      1
+/* 0 = IP checksum, 1 = CRC */
+#define TDIF_TASK_CONTEXT_HOSTGUARDTYPE_MASK            0x1
+#define TDIF_TASK_CONTEXT_HOSTGUARDTYPE_SHIFT           2
+#define TDIF_TASK_CONTEXT_SETERRORWITHEOP_MASK          0x1
+#define TDIF_TASK_CONTEXT_SETERRORWITHEOP_SHIFT         3
+/* 1/2/3 - Protection Type */
+#define TDIF_TASK_CONTEXT_PROTECTIONTYPE_MASK           0x3
+#define TDIF_TASK_CONTEXT_PROTECTIONTYPE_SHIFT          4
+/* 0=0x0000, 1=0xffff */
+#define TDIF_TASK_CONTEXT_CRC_SEED_MASK                 0x1
+#define TDIF_TASK_CONTEXT_CRC_SEED_SHIFT                6
+#define TDIF_TASK_CONTEXT_RESERVED2_MASK                0x1
+#define TDIF_TASK_CONTEXT_RESERVED2_SHIFT               7
+	__le32 flags1;
+#define TDIF_TASK_CONTEXT_VALIDATEGUARD_MASK            0x1
+#define TDIF_TASK_CONTEXT_VALIDATEGUARD_SHIFT           0
+#define TDIF_TASK_CONTEXT_VALIDATEAPPTAG_MASK           0x1
+#define TDIF_TASK_CONTEXT_VALIDATEAPPTAG_SHIFT          1
+#define TDIF_TASK_CONTEXT_VALIDATEREFTAG_MASK           0x1
+#define TDIF_TASK_CONTEXT_VALIDATEREFTAG_SHIFT          2
+#define TDIF_TASK_CONTEXT_FORWARDGUARD_MASK             0x1
+#define TDIF_TASK_CONTEXT_FORWARDGUARD_SHIFT            3
+#define TDIF_TASK_CONTEXT_FORWARDAPPTAG_MASK            0x1
+#define TDIF_TASK_CONTEXT_FORWARDAPPTAG_SHIFT           4
+#define TDIF_TASK_CONTEXT_FORWARDREFTAG_MASK            0x1
+#define TDIF_TASK_CONTEXT_FORWARDREFTAG_SHIFT           5
+/* 0=512B, 1=1KB, 2=2KB, 3=4KB, 4=8KB */
+#define TDIF_TASK_CONTEXT_INTERVALSIZE_MASK             0x7
+#define TDIF_TASK_CONTEXT_INTERVALSIZE_SHIFT            6
+/* 0=None, 1=DIF, 2=DIX */
+#define TDIF_TASK_CONTEXT_HOSTINTERFACE_MASK            0x3
+#define TDIF_TASK_CONTEXT_HOSTINTERFACE_SHIFT           9
+/* DIF tag right at the beginning of DIF interval */
+#define TDIF_TASK_CONTEXT_DIFBEFOREDATA_MASK            0x1
+#define TDIF_TASK_CONTEXT_DIFBEFOREDATA_SHIFT           11
+/* reserved */
+#define TDIF_TASK_CONTEXT_RESERVED3_MASK                0x1
+#define TDIF_TASK_CONTEXT_RESERVED3_SHIFT               12
+/* 0=None, 1=DIF */
+#define TDIF_TASK_CONTEXT_NETWORKINTERFACE_MASK         0x1
+#define TDIF_TASK_CONTEXT_NETWORKINTERFACE_SHIFT        13
+#define TDIF_TASK_CONTEXT_RECEIVEDDIFBYTESLEFTA_MASK    0xF
+#define TDIF_TASK_CONTEXT_RECEIVEDDIFBYTESLEFTA_SHIFT   14
+#define TDIF_TASK_CONTEXT_TRANSMITEDDIFBYTESLEFTA_MASK  0xF
+#define TDIF_TASK_CONTEXT_TRANSMITEDDIFBYTESLEFTA_SHIFT 18
+#define TDIF_TASK_CONTEXT_ERRORINIOA_MASK               0x1
+#define TDIF_TASK_CONTEXT_ERRORINIOA_SHIFT              22
+#define TDIF_TASK_CONTEXT_CHECKSUMOVERFLOWA_MASK        0x1
+#define TDIF_TASK_CONTEXT_CHECKSUMOVERFLOWA_SHIFT       23
+/* mask for refernce tag handling */
+#define TDIF_TASK_CONTEXT_REFTAGMASK_MASK               0xF
+#define TDIF_TASK_CONTEXT_REFTAGMASK_SHIFT              24
+/* Forward application tag with mask */
+#define TDIF_TASK_CONTEXT_FORWARDAPPTAGWITHMASK_MASK    0x1
+#define TDIF_TASK_CONTEXT_FORWARDAPPTAGWITHMASK_SHIFT   28
+/* Forward reference tag with mask */
+#define TDIF_TASK_CONTEXT_FORWARDREFTAGWITHMASK_MASK    0x1
+#define TDIF_TASK_CONTEXT_FORWARDREFTAGWITHMASK_SHIFT   29
+/* Keep reference tag constant */
+#define TDIF_TASK_CONTEXT_KEEPREFTAGCONST_MASK          0x1
+#define TDIF_TASK_CONTEXT_KEEPREFTAGCONST_SHIFT         30
+#define TDIF_TASK_CONTEXT_RESERVED4_MASK                0x1
+#define TDIF_TASK_CONTEXT_RESERVED4_SHIFT               31
+	__le32 offsetInIOB;
+	__le16 partialCrcValueA;
+	__le16 partialChecksumValueA;
+	__le32 offsetInIOA;
+	u8 partialDifDataA[8];
+	u8 partialDifDataB[8];
+};
+
+
+/*
+ * Timers context
+ */
+struct timers_context {
+	__le32 logical_client_0;
+/* Expiration time of logical client 0 */
+#define TIMERS_CONTEXT_EXPIRATIONTIMELC0_MASK     0xFFFFFFF
+#define TIMERS_CONTEXT_EXPIRATIONTIMELC0_SHIFT    0
+/* Valid bit of logical client 0 */
+#define TIMERS_CONTEXT_VALIDLC0_MASK              0x1
+#define TIMERS_CONTEXT_VALIDLC0_SHIFT             28
+/* Active bit of logical client 0 */
+#define TIMERS_CONTEXT_ACTIVELC0_MASK             0x1
+#define TIMERS_CONTEXT_ACTIVELC0_SHIFT            29
+#define TIMERS_CONTEXT_RESERVED0_MASK             0x3
+#define TIMERS_CONTEXT_RESERVED0_SHIFT            30
+	__le32 logical_client_1;
+/* Expiration time of logical client 1 */
+#define TIMERS_CONTEXT_EXPIRATIONTIMELC1_MASK     0xFFFFFFF
+#define TIMERS_CONTEXT_EXPIRATIONTIMELC1_SHIFT    0
+/* Valid bit of logical client 1 */
+#define TIMERS_CONTEXT_VALIDLC1_MASK              0x1
+#define TIMERS_CONTEXT_VALIDLC1_SHIFT             28
+/* Active bit of logical client 1 */
+#define TIMERS_CONTEXT_ACTIVELC1_MASK             0x1
+#define TIMERS_CONTEXT_ACTIVELC1_SHIFT            29
+#define TIMERS_CONTEXT_RESERVED1_MASK             0x3
+#define TIMERS_CONTEXT_RESERVED1_SHIFT            30
+	__le32 logical_client_2;
+/* Expiration time of logical client 2 */
+#define TIMERS_CONTEXT_EXPIRATIONTIMELC2_MASK     0xFFFFFFF
+#define TIMERS_CONTEXT_EXPIRATIONTIMELC2_SHIFT    0
+/* Valid bit of logical client 2 */
+#define TIMERS_CONTEXT_VALIDLC2_MASK              0x1
+#define TIMERS_CONTEXT_VALIDLC2_SHIFT             28
+/* Active bit of logical client 2 */
+#define TIMERS_CONTEXT_ACTIVELC2_MASK             0x1
+#define TIMERS_CONTEXT_ACTIVELC2_SHIFT            29
+#define TIMERS_CONTEXT_RESERVED2_MASK             0x3
+#define TIMERS_CONTEXT_RESERVED2_SHIFT            30
+	__le32 host_expiration_fields;
+/* Expiration time on host (closest one) */
+#define TIMERS_CONTEXT_HOSTEXPRIRATIONVALUE_MASK  0xFFFFFFF
+#define TIMERS_CONTEXT_HOSTEXPRIRATIONVALUE_SHIFT 0
+/* Valid bit of host expiration */
+#define TIMERS_CONTEXT_HOSTEXPRIRATIONVALID_MASK  0x1
+#define TIMERS_CONTEXT_HOSTEXPRIRATIONVALID_SHIFT 28
+#define TIMERS_CONTEXT_RESERVED3_MASK             0x7
+#define TIMERS_CONTEXT_RESERVED3_SHIFT            29
+};
+
+
+/*
+ * Enum for next_protocol field of tunnel_parsing_flags
+ */
+enum tunnel_next_protocol {
+	e_unknown = 0,
+	e_l2 = 1,
+	e_ipv4 = 2,
+	e_ipv6 = 3,
+	MAX_TUNNEL_NEXT_PROTOCOL
+};
 
 #endif /* __COMMON_HSI__ */
diff --git a/drivers/net/qede/base/ecore_dev.c b/drivers/net/qede/base/ecore_dev.c
index 46d3e80..9e32279 100644
--- a/drivers/net/qede/base/ecore_dev.c
+++ b/drivers/net/qede/base/ecore_dev.c
@@ -3056,8 +3056,6 @@ static enum _ecore_status_t ecore_set_coalesce(struct ecore_hwfn *p_hwfn,
 
 	OSAL_MEMSET(p_qzone, 0, qzone_size);
 	p_coalesce_timeset = p_qzone;
-	p_coalesce_timeset->timeset = timeset;
-	p_coalesce_timeset->valid = 1;
 	ecore_memcpy_to(p_hwfn, p_ptt, hw_addr, p_qzone, qzone_size);
 
 	return ECORE_SUCCESS;
diff --git a/drivers/net/qede/base/ecore_hsi_common.h b/drivers/net/qede/base/ecore_hsi_common.h
index 877de8b..3c4d7c0 100644
--- a/drivers/net/qede/base/ecore_hsi_common.h
+++ b/drivers/net/qede/base/ecore_hsi_common.h
@@ -25,6 +25,7 @@ enum common_event_opcode {
 	COMMON_EVENT_VF_FLR,
 	COMMON_EVENT_PF_UPDATE,
 	COMMON_EVENT_MALICIOUS_VF,
+	COMMON_EVENT_RL_UPDATE,
 	COMMON_EVENT_EMPTY,
 	MAX_COMMON_EVENT_OPCODE
 };
@@ -39,6 +40,7 @@ enum common_ramrod_cmd_id {
 	COMMON_RAMROD_VF_START /* VF Function Start */,
 	COMMON_RAMROD_VF_STOP /* VF Function Stop Ramrod */,
 	COMMON_RAMROD_PF_UPDATE /* PF update Ramrod */,
+	COMMON_RAMROD_RL_UPDATE /* QCN/DCQCN RL update Ramrod */,
 	COMMON_RAMROD_EMPTY /* Empty Ramrod */,
 	MAX_COMMON_RAMROD_CMD_ID
 };
@@ -643,6 +645,15 @@ enum core_ramrod_cmd_id {
 };
 
 /*
+ * Core RX CQE Type for Light L2
+ */
+enum core_roce_flavor_type {
+	CORE_ROCE,
+	CORE_RROCE,
+	MAX_CORE_ROCE_FLAVOR_TYPE
+};
+
+/*
  * Specifies how ll2 should deal with packets errors: packet_too_big and no_buff
  */
 struct core_rx_action_on_error {
@@ -814,10 +825,32 @@ struct core_tx_bd_flags {
 struct core_tx_bd {
 	struct regpair addr /* Buffer Address */;
 	__le16 nbytes /* Number of Bytes in Buffer */;
-	__le16 vlan /* VLAN to insert to packet (if insertion flag set) */;
-	u8 nbds /* Number of BDs that make up one packet */;
+/* Network packets: VLAN to insert to packet (if insertion flag set) LoopBack
+ * packets: echo data to pass to Rx
+ */
+	__le16 nw_vlan_or_lb_echo;
+	u8 bitfield0;
+/* Number of BDs that make up one packet - width wide enough to present
+ * X_CORE_LL2_NUM_OF_BDS_ON_ST_CT
+ */
+#define CORE_TX_BD_NBDS_MASK             0xF
+#define CORE_TX_BD_NBDS_SHIFT            0
+/* Use roce_flavor enum - Diffrentiate between Roce flavors is valid when
+ * connType is ROCE (use enum core_roce_flavor_type)
+ */
+#define CORE_TX_BD_ROCE_FLAV_MASK        0x1
+#define CORE_TX_BD_ROCE_FLAV_SHIFT       4
+#define CORE_TX_BD_RESERVED0_MASK        0x7
+#define CORE_TX_BD_RESERVED0_SHIFT       5
 	struct core_tx_bd_flags bd_flags /* BD Flags */;
-	__le16 l4_hdr_offset_w;
+	__le16 bitfield1;
+#define CORE_TX_BD_L4_HDR_OFFSET_W_MASK  0x3FFF
+#define CORE_TX_BD_L4_HDR_OFFSET_W_SHIFT 0
+/* Packet destination - Network, LB (use enum core_tx_dest) */
+#define CORE_TX_BD_TX_DST_MASK           0x1
+#define CORE_TX_BD_TX_DST_SHIFT          14
+#define CORE_TX_BD_RESERVED1_MASK        0x1
+#define CORE_TX_BD_RESERVED1_SHIFT       15
 };
 
 /*
@@ -830,22 +863,21 @@ enum core_tx_dest {
 };
 
 /*
- * Ramrod data for rx queue start ramrod
+ * Ramrod data for tx queue start ramrod
  */
 struct core_tx_start_ramrod_data {
 	struct regpair pbl_base_addr /* Address of the pbl page */;
 	__le16 mtu /* Maximum transmission unit */;
 	__le16 sb_id /* Status block ID */;
 	u8 sb_index /* Status block protocol index */;
-	u8 tx_dest /* TX Destination (either Network or LB) */;
 	u8 stats_en /* Statistics Enable */;
 	u8 stats_id /* Statistics Counter ID */;
+	u8 conn_type /* connection type that loaded ll2 */;
 	__le16 pbl_size /* Number of BD pages pointed by PBL */;
 	__le16 qm_pq_id /* QM PQ ID */;
-	u8 conn_type /* connection type that loaded ll2 */;
 	u8 gsi_offload_flag
 	    /* set when in GSI offload mode on ROCE connection */;
-	u8 resrved[2];
+	u8 resrved[3];
 };
 
 /*
@@ -855,6 +887,25 @@ struct core_tx_stop_ramrod_data {
 	__le32 reserved0[2];
 };
 
+/*
+ * Enum flag for what type of dcb data to update
+ */
+enum dcb_dhcp_update_flag {
+/* use when no change should be done to dcb data */
+	DONT_UPDATE_DCB_DHCP,
+	UPDATE_DCB /* use to update only l2 (vlan) priority */,
+	UPDATE_DSCP /* use to update only l3 dhcp */,
+	UPDATE_DCB_DSCP /* update vlan pri and dhcp */,
+	MAX_DCB_DHCP_UPDATE_FLAG
+};
+
+struct eth_mstorm_per_pf_stat {
+	struct regpair gre_discard_pkts /* Dropped GRE RX packets */;
+	struct regpair vxlan_discard_pkts /* Dropped VXLAN RX packets */;
+	struct regpair geneve_discard_pkts /* Dropped GENEVE RX packets */;
+	struct regpair lb_discard_pkts /* Dropped Tx switched packets */;
+};
+
 struct eth_mstorm_per_queue_stat {
 	struct regpair ttl0_discard;
 	struct regpair packet_too_big_discard;
@@ -867,6 +918,33 @@ struct eth_mstorm_per_queue_stat {
 };
 
 /*
+ * Ethernet TX Per PF
+ */
+struct eth_pstorm_per_pf_stat {
+/* number of total ucast bytes sent on loopback port without errors */
+	struct regpair sent_lb_ucast_bytes;
+/* number of total mcast bytes sent on loopback port without errors */
+	struct regpair sent_lb_mcast_bytes;
+/* number of total bcast bytes sent on loopback port without errors */
+	struct regpair sent_lb_bcast_bytes;
+/* number of total ucast packets sent on loopback port without errors */
+	struct regpair sent_lb_ucast_pkts;
+/* number of total mcast packets sent on loopback port without errors */
+	struct regpair sent_lb_mcast_pkts;
+/* number of total bcast packets sent on loopback port without errors */
+	struct regpair sent_lb_bcast_pkts;
+	struct regpair sent_gre_bytes /* Sent GRE bytes */;
+	struct regpair sent_vxlan_bytes /* Sent VXLAN bytes */;
+	struct regpair sent_geneve_bytes /* Sent GENEVE bytes */;
+	struct regpair sent_gre_pkts /* Sent GRE packets */;
+	struct regpair sent_vxlan_pkts /* Sent VXLAN packets */;
+	struct regpair sent_geneve_pkts /* Sent GENEVE packets */;
+	struct regpair gre_drop_pkts /* Dropped GRE TX packets */;
+	struct regpair vxlan_drop_pkts /* Dropped VXLAN TX packets */;
+	struct regpair geneve_drop_pkts /* Dropped GENEVE TX packets */;
+};
+
+/*
  * Ethernet TX Per Queue Stats
  */
 struct eth_pstorm_per_queue_stat {
@@ -898,6 +976,27 @@ struct eth_rx_rate_limit {
 	__le16 reserved1;
 };
 
+struct eth_ustorm_per_pf_stat {
+/* number of total ucast bytes received on loopback port without errors */
+	struct regpair rcv_lb_ucast_bytes;
+/* number of total mcast bytes received on loopback port without errors */
+	struct regpair rcv_lb_mcast_bytes;
+/* number of total bcast bytes received on loopback port without errors */
+	struct regpair rcv_lb_bcast_bytes;
+/* number of total ucast packets received on loopback port without errors */
+	struct regpair rcv_lb_ucast_pkts;
+/* number of total mcast packets received on loopback port without errors */
+	struct regpair rcv_lb_mcast_pkts;
+/* number of total bcast packets received on loopback port without errors */
+	struct regpair rcv_lb_bcast_pkts;
+	struct regpair rcv_gre_bytes /* Received GRE bytes */;
+	struct regpair rcv_vxlan_bytes /* Received VXLAN bytes */;
+	struct regpair rcv_geneve_bytes /* Received GENEVE bytes */;
+	struct regpair rcv_gre_pkts /* Received GRE packets */;
+	struct regpair rcv_vxlan_pkts /* Received VXLAN packets */;
+	struct regpair rcv_geneve_pkts /* Received GENEVE packets */;
+};
+
 struct eth_ustorm_per_queue_stat {
 	struct regpair rcv_ucast_bytes;
 	struct regpair rcv_mcast_bytes;
@@ -934,6 +1033,14 @@ enum fw_flow_ctrl_mode {
 };
 
 /*
+ * Major and Minor hsi Versions
+ */
+struct hsi_fp_ver_struct {
+	u8 minor_ver_arr[2] /* Minor Version of hsi loading pf */;
+	u8 major_ver_arr[2] /* Major Version of driver loading pf */;
+};
+
+/*
  * Integration Phase
  */
 enum integ_phase {
@@ -944,6 +1051,18 @@ enum integ_phase {
 };
 
 /*
+ * Ports mode
+ */
+enum iwarp_ll2_tx_queues {
+/* LL2 queue for OOO packets sent in-order by the driver */
+	IWARP_LL2_IN_ORDER_TX_QUEUE = 1,
+/* LL2 queue for unaligned packets sent aligned by the driver */
+	IWARP_LL2_ALIGNED_TX_QUEUE,
+	IWARP_LL2_ERROR /* Error indication */,
+	MAX_IWARP_LL2_TX_QUEUES
+};
+
+/*
  * Malicious VF error ID
  */
 enum malicious_vf_error_id {
@@ -953,7 +1072,7 @@ enum malicious_vf_error_id {
 	VF_ZONE_MSG_NOT_VALID /* VF channel message is not valid */,
 	VF_ZONE_FUNC_NOT_ENABLED /* Parent PF of VF channel is not active */,
 	ETH_PACKET_TOO_SMALL
-/* TX packet is shorter then reported on BDs or from minimal size */
+	    /* TX packet is shorter then reported on BDs or from minimal size */
 	    ,
 	ETH_ILLEGAL_VLAN_MODE
 	    /* Tx packet with marked as insert VLAN when its illegal */,
@@ -975,6 +1094,7 @@ enum malicious_vf_error_id {
 	ETH_EDPM_OUT_OF_SYNC /* Valid BDs on local ring after EDPM L2 sync */,
 	ETH_TUNN_IPV6_EXT_NBD_ERR
 	    /* Tunneled packet with IPv6+Ext without a proper number of BDs */,
+	ETH_CONTROL_PACKET_VIOLATION /* VF sent control frame such as PFC */,
 	MAX_MALICIOUS_VF_ERROR_ID
 };
 
@@ -984,6 +1104,9 @@ enum malicious_vf_error_id {
 struct mstorm_non_trigger_vf_zone {
 	struct eth_mstorm_per_queue_stat eth_queue_stat
 	    /* VF statistic bucket */;
+/* VF RX queues producers */
+	struct eth_rx_prod_data
+		eth_rx_queue_producers[ETH_MAX_NUM_RX_QUEUES_PER_VF_QUAD];
 };
 
 /*
@@ -1060,10 +1183,11 @@ struct pf_start_ramrod_data {
 	u8 allow_npar_tx_switching;
 	u8 inner_to_outer_pri_map[8];
 	u8 pri_map_valid
-/* If inner_to_outer_pri_map is initialize then set pri_map_valid */
+	    /* If inner_to_outer_pri_map is initialize then set pri_map_valid */
 	  ;
 	__le32 outer_tag;
-	u8 reserved0[4];
+/* FP HSI version to be used by FW */
+	struct hsi_fp_ver_struct hsi_fp_ver;
 };
 
 /*
@@ -1071,9 +1195,11 @@ struct pf_start_ramrod_data {
  */
 struct protocol_dcb_data {
 	u8 dcb_enable_flag /* dcbEnable flag value */;
+	u8 dscp_enable_flag /* If set use dscp value */;
 	u8 dcb_priority /* dcbPri flag value */;
 	u8 dcb_tc /* dcb TC value */;
-	u8 reserved;
+	u8 dscp_val /* dscp value to write if dscp_enable_flag is set */;
+	u8 reserved0;
 };
 
 /*
@@ -1081,6 +1207,14 @@ struct protocol_dcb_data {
  */
 struct pf_update_tunnel_config {
 	u8 update_rx_pf_clss;
+/* Update per PORT default tunnel RX classification scheme for traffic with
+ * unknown unicast outer MAC in NPAR mode.
+ */
+	u8 update_rx_def_ucast_clss;
+/* Update per PORT default tunnel RX classification scheme for traffic with non
+ * unicast outer MAC in NPAR mode.
+ */
+	u8 update_rx_def_non_ucast_clss;
 	u8 update_tx_pf_clss;
 	u8 set_vxlan_udp_port_flg
 	    /* Update VXLAN tunnel UDP destination port. */;
@@ -1102,7 +1236,7 @@ struct pf_update_tunnel_config {
 	u8 tunnel_clss_ipgre /* Classification scheme for ip GRE tunnel. */;
 	__le16 vxlan_udp_port /* VXLAN tunnel UDP destination port. */;
 	__le16 geneve_udp_port /* GENEVE tunnel UDP destination port. */;
-	__le16 reserved[3];
+	__le16 reserved[2];
 };
 
 /*
@@ -1114,9 +1248,10 @@ struct pf_update_ramrod_data {
 	u8 update_fcoe_dcb_data_flag /* Update FCOE DCB  data indication */;
 	u8 update_iscsi_dcb_data_flag /* Update iSCSI DCB  data indication */;
 	u8 update_roce_dcb_data_flag /* Update ROCE DCB  data indication */;
+/* Update RROCE (RoceV2) DCB  data indication */
+	u8 update_rroce_dcb_data_flag;
 	u8 update_iwarp_dcb_data_flag /* Update IWARP DCB  data indication */;
 	u8 update_mf_vlan_flag /* Update MF outer vlan Id */;
-	u8 reserved;
 	struct protocol_dcb_data eth_dcb_data /* core eth related fields */;
 	struct protocol_dcb_data fcoe_dcb_data /* core fcoe related fields */;
 	struct protocol_dcb_data iscsi_dcb_data /* core iscsi related fields */
@@ -1124,10 +1259,12 @@ struct pf_update_ramrod_data {
 	struct protocol_dcb_data roce_dcb_data /* core roce related fields */;
 	struct protocol_dcb_data iwarp_dcb_data /* core iwarp related fields */
 	  ;
+/* core roce related fields */
+	struct protocol_dcb_data rroce_dcb_data;
 	__le16 mf_vlan /* new outer vlan id value */;
-	__le16 reserved2;
-	struct pf_update_tunnel_config tunnel_config /* tunnel configuration. */
-	  ;
+	__le16 reserved;
+/* tunnel configuration. */
+	struct pf_update_tunnel_config tunnel_config;
 };
 
 /*
@@ -1143,6 +1280,15 @@ enum ports_mode {
 };
 
 /*
+ * use to index in hsi_fp_[major|minor]_ver_arr per protocol
+ */
+enum protocol_version_array_key {
+	ETH_VER_KEY = 0,
+	ROCE_VER_KEY,
+	MAX_PROTOCOL_VERSION_ARRAY_KEY
+};
+
+/*
  * RDMA TX Stats
  */
 struct rdma_sent_stats {
@@ -1187,6 +1333,31 @@ struct rdma_rcv_stats {
 };
 
 /*
+ * Data for update QCN/DCQCN RL ramrod
+ */
+struct rl_update_ramrod_data {
+	u8 qcn_update_param_flg /* Update QCN global params: timeout. */;
+/* Update DCQCN global params: timeout, g, k. */
+	u8 dcqcn_update_param_flg;
+	u8 rl_init_flg /* Init RL parameters, when RL disabled. */;
+	u8 rl_start_flg /* Start RL in IDLE state. Set rate to maximum. */;
+	u8 rl_stop_flg /* Stop RL. */;
+	u8 rl_id_first /* ID of first or single RL, that will be updated. */;
+/* ID of last RL, that will be updated. If clear, single RL will updated. */
+	u8 rl_id_last;
+	u8 rl_dc_qcn_flg /* If set, RL will used for DCQCN. */;
+	__le32 rl_bc_rate /* Byte Counter Limit. */;
+	__le16 rl_max_rate /* Maximum rate in 1.6 Mbps resolution. */;
+	__le16 rl_r_ai /* Active increase rate. */;
+	__le16 rl_r_hai /* Hyper active increase rate. */;
+	__le16 dcqcn_g /* DCQCN Alpha update gain in 1/64K resolution . */;
+	__le32 dcqcn_k_us /* DCQCN Alpha update interval. */;
+	__le32 dcqcn_timeuot_us /* DCQCN timeout. */;
+	__le32 qcn_timeuot_us /* QCN timeout. */;
+	__le32 reserved[2];
+};
+
+/*
  * Slowpath Element (SPQE)
  */
 struct slow_path_element {
@@ -1223,6 +1394,11 @@ struct tstorm_per_port_stat {
 	  ;
 	struct regpair preroce_irregular_pkt
 	    /* packet is an PREROCE irregular packet */;
+	struct regpair eth_gre_tunn_filter_discard /* GRE dropped packets */;
+/* VXLAN dropped packets */
+	struct regpair eth_vxlan_tunn_filter_discard;
+/* GENEVE dropped packets */
+	struct regpair eth_geneve_tunn_filter_discard;
 };
 
 /*
@@ -1244,10 +1420,14 @@ enum tunnel_clss {
 	TUNNEL_CLSS_MAC_VNI
 	    ,
 	TUNNEL_CLSS_INNER_MAC_VLAN
-/* Use MAC and VLAN from last L2 header for vport classification */
+	    /* Use MAC and VLAN from last L2 header for vport classification */
 	    ,
 	TUNNEL_CLSS_INNER_MAC_VNI
 	    ,
+/* Use MAC and VLAN from last L2 header for vport classification. If no exact
+ * match, use MAC and VLAN from first L2 header for classification.
+ */
+	TUNNEL_CLSS_MAC_VLAN_DUAL_STAGE,
 	MAX_TUNNEL_CLSS
 };
 
@@ -1295,7 +1475,9 @@ struct vf_start_ramrod_data {
 	u8 enable_flr_ack;
 	__le16 opaque_fid /* VF opaque FID */;
 	u8 personality /* define what type of personality is new VF */;
-	u8 reserved[3];
+	u8 reserved[7];
+/* FP HSI version to be used by FW */
+	struct hsi_fp_ver_struct hsi_fp_ver;
 };
 
 /*
@@ -1309,6 +1491,19 @@ struct vf_stop_ramrod_data {
 };
 
 /*
+ * VF zone size mode.
+ */
+enum vf_zone_size_mode {
+/* Default VF zone size. Up to 192 VF supported. */
+	VF_ZONE_SIZE_MODE_DEFAULT,
+/* Doubled VF zone size. Up to 96 VF supported. */
+	VF_ZONE_SIZE_MODE_DOUBLE,
+/* Quad VF zone size. Up to 48 VF supported. */
+	VF_ZONE_SIZE_MODE_QUAD,
+	MAX_VF_ZONE_SIZE_MODE
+};
+
+/*
  * Attentions status block
  */
 struct atten_status_block {
@@ -1319,6 +1514,7 @@ struct atten_status_block {
 	__le32 reserved1;
 };
 
+
 /*
  * Igu cleanup bit values to distinguish between clean or producer consumer
  */
@@ -1376,7 +1572,7 @@ struct dmae_cmd {
 	__le32 src_addr_hi;
 	__le32 dst_addr_lo;
 	__le32 dst_addr_hi;
-	__le16 length /* Length in DW */;
+	__le16 length_dw /* Length in DW */;
 	__le16 opcode_b;
 #define DMAE_CMD_SRC_VF_ID_MASK        0xFF
 #define DMAE_CMD_SRC_VF_ID_SHIFT       0
@@ -1395,10 +1591,62 @@ struct dmae_cmd {
 	__le16 xsum8 /* checksum8 result  */;
 };
 
-struct storm_ram_section {
-	__le16 offset
-	    /* The offset of the section in the RAM (in 64 bit units) */;
-	__le16 size /* The size of the section (in 64 bit units) */;
+
+enum dmae_cmd_comp_crc_en_enum {
+	dmae_cmd_comp_crc_disabled /* Do not write a CRC word */,
+	dmae_cmd_comp_crc_enabled /* Write a CRC word */,
+	MAX_DMAE_CMD_COMP_CRC_EN_ENUM
+};
+
+
+enum dmae_cmd_comp_func_enum {
+/* completion word and/or CRC will be sent to SRC-PCI function/SRC VFID */
+	dmae_cmd_comp_func_to_src,
+/* completion word and/or CRC will be sent to DST-PCI function/DST VFID */
+	dmae_cmd_comp_func_to_dst,
+	MAX_DMAE_CMD_COMP_FUNC_ENUM
+};
+
+
+enum dmae_cmd_comp_word_en_enum {
+	dmae_cmd_comp_word_disabled /* Do not write a completion word */,
+	dmae_cmd_comp_word_enabled /* Write the completion word */,
+	MAX_DMAE_CMD_COMP_WORD_EN_ENUM
+};
+
+
+enum dmae_cmd_c_dst_enum {
+	dmae_cmd_c_dst_pcie,
+	dmae_cmd_c_dst_grc,
+	MAX_DMAE_CMD_C_DST_ENUM
+};
+
+
+enum dmae_cmd_dst_enum {
+	dmae_cmd_dst_none_0,
+	dmae_cmd_dst_pcie,
+	dmae_cmd_dst_grc,
+	dmae_cmd_dst_none_3,
+	MAX_DMAE_CMD_DST_ENUM
+};
+
+
+enum dmae_cmd_error_handling_enum {
+/* Send a regular completion (with no error indication) */
+	dmae_cmd_error_handling_send_regular_comp,
+/* Send a completion with an error indication (i.e. set bit 31 of the completion
+ * word)
+ */
+	dmae_cmd_error_handling_send_comp_with_err,
+	dmae_cmd_error_handling_dont_send_comp /* Do not send a completion */,
+	MAX_DMAE_CMD_ERROR_HANDLING_ENUM
+};
+
+
+enum dmae_cmd_src_enum {
+	dmae_cmd_src_pcie /* The source is the PCIe */,
+	dmae_cmd_src_grc /* The source is the GRC */,
+	MAX_DMAE_CMD_SRC_ENUM
 };
 
 /*
@@ -1475,6 +1723,7 @@ struct igu_msix_vector {
 #define IGU_MSIX_VECTOR_RESERVED1_SHIFT    24
 };
 
+
 struct mstorm_core_conn_ag_ctx {
 	u8 byte0 /* cdu_validation */;
 	u8 byte1 /* state */;
diff --git a/drivers/net/qede/base/ecore_hw.c b/drivers/net/qede/base/ecore_hw.c
index e9b96d5..72bc6de 100644
--- a/drivers/net/qede/base/ecore_hw.c
+++ b/drivers/net/qede/base/ecore_hw.c
@@ -461,7 +461,7 @@ ecore_dmae_post_command(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
 			  " src=0x%x:%x dst=0x%x:%x\n",
 			  idx_cmd, (u32)p_command->opcode,
 			  (u16)p_command->opcode_b,
-			  (int)p_command->length,
+			  (int)p_command->length_dw,
 			  (int)p_command->src_addr_hi,
 			  (int)p_command->src_addr_lo,
 			  (int)p_command->dst_addr_hi,
@@ -668,7 +668,7 @@ ecore_dmae_execute_sub_operation(struct ecore_hwfn *p_hwfn,
 		return ECORE_INVAL;
 	}
 
-	cmd->length = (u16)length;
+	cmd->length_dw = (u16)length;
 
 	if (src_type == ECORE_DMAE_ADDRESS_HOST_VIRT ||
 	    src_type == ECORE_DMAE_ADDRESS_HOST_PHYS)
diff --git a/drivers/net/qede/base/eth_common.h b/drivers/net/qede/base/eth_common.h
index 71ef615..bd73f7d 100644
--- a/drivers/net/qede/base/eth_common.h
+++ b/drivers/net/qede/base/eth_common.h
@@ -59,14 +59,6 @@
 #define ETH_TPA_CQE_END_LEN_LIST_SIZE     4
 
 /*
- * Interrupt coalescing TimeSet
- */
-struct coalescing_timeset {
-	u8 timeset;
-	u8 valid /* Only if this flag is set, timeset will take effect */;
-};
-
-/*
  * Destination port mode
  */
 enum dest_port_mode {
@@ -364,16 +356,6 @@ struct eth_rx_pmd_cqe {
 };
 
 /*
- * ETH Rx producers data
- */
-struct eth_rx_prod_data {
-	__le16 bd_prod /* BD producer */;
-	__le16 cqe_prod /* CQE producer */;
-	__le16 reserved;
-	__le16 reserved1 /* FW reserved. */;
-};
-
-/*
  * Aggregation end reason.
  */
 enum eth_tpa_end_reason {
@@ -487,15 +469,6 @@ struct mstorm_eth_queue_zone {
 };
 
 /*
- * Ustorm Queue Zone
- */
-struct ustorm_eth_queue_zone {
-	struct coalescing_timeset int_coalescing_timeset
-	    /* Rx interrupt coalescing TimeSet */;
-	__le16 reserved[3];
-};
-
-/*
  * Ystorm Queue Zone
  */
 struct ystorm_eth_queue_zone {
diff --git a/drivers/net/qede/base/reg_addr.h b/drivers/net/qede/base/reg_addr.h
index 3b25e1a..ab88671 100644
--- a/drivers/net/qede/base/reg_addr.h
+++ b/drivers/net/qede/base/reg_addr.h
@@ -6,6 +6,14 @@
  * See LICENSE.qede_pmd for copyright and licensing details.
  */
 
+/*
+ * Copyright (c) 2016 QLogic Corporation.
+ * All rights reserved.
+ * www.qlogic.com
+ *
+ * See LICENSE.qede_pmd for copyright and licensing details.
+ */
+
 #define  CDU_REG_CID_ADDR_PARAMS_CONTEXT_SIZE_SHIFT \
 	0
 
@@ -1105,3 +1113,31 @@
 #define CDU_REG_SEGMENT1_PARAMS_T1_TID_SIZE_SHIFT 24
 #define CDU_REG_SEGMENT1_PARAMS_T1_TID_BLOCK_WASTE_SHIFT 16
 #define DORQ_REG_DB_DROP_DETAILS_ADDRESS 0x100a1cUL
+
+/* 8.10.9.0 FW */
+#define NIG_REG_VXLAN_CTRL 0x50105cUL
+#define PRS_REG_SEARCH_ROCE 0x1f040cUL
+#define PRS_REG_CM_HDR_GFT 0x1f11c8UL
+#define PRS_REG_CM_HDR_GFT_EVENT_ID_SHIFT 0
+#define PRS_REG_CM_HDR_GFT_CM_HDR_SHIFT 8
+#define CCFC_REG_WEAK_ENABLE_VF 0x2e0704UL
+#define TCFC_REG_STRONG_ENABLE_VF 0x2d070cUL
+#define TCFC_REG_WEAK_ENABLE_VF 0x2d0704UL
+#define PRS_REG_SEARCH_GFT 0x1f11bcUL
+#define PRS_REG_LOAD_L2_FILTER 0x1f0198UL
+#define PRS_REG_GFT_CAM 0x1f1100UL
+#define PRS_REG_GFT_PROFILE_MASK_RAM 0x1f1000UL
+#define PGLUE_B_REG_MSDM_VF_SHIFT_B 0x2aa1c4UL
+#define PGLUE_B_REG_MSDM_OFFSET_MASK_B 0x2aa1c0UL
+#define PRS_REG_PKT_LEN_STAT_TAGS_NOT_COUNTED_FIRST 0x1f0a0cUL
+#define PRS_REG_SEARCH_FCOE 0x1f0408UL
+#define PGLUE_B_REG_PGL_ADDR_E8_F0 0x2aaf98UL
+#define NIG_REG_DSCP_TO_TC_MAP_ENABLE 0x5088f8UL
+#define PGLUE_B_REG_PGL_ADDR_EC_F0 0x2aaf9cUL
+#define PGLUE_B_REG_PGL_ADDR_F0_F0 0x2aafa0UL
+#define PRS_REG_ROCE_DEST_QP_MAX_PF 0x1f0430UL
+#define PGLUE_B_REG_PGL_ADDR_F4_F0 0x2aafa4UL
+#define IGU_REG_WRITE_DONE_PENDING 0x180900UL
+#define NIG_REG_LLH_TAGMAC_DEF_PF_VECTOR 0x50196cUL
+#define PRS_REG_MSG_INFO 0x1f0a1cUL
+#define BAR0_MAP_REG_XSDM_RAM 0x1e00000UL
