diff mbox

[dpdk-dev] ixgbe: fix bad shift operation in ixgbe_set_pool_tx

Message ID 1460730779-8200-1-git-send-email-tomaszx.kulasek@intel.com (mailing list archive)
State Superseded, archived
Delegated to: Bruce Richardson
Headers

Commit Message

Tomasz Kulasek April 15, 2016, 2:32 p.m. UTC 
  CID 13190 (#1 of 1): Bad bit shift operation (BAD_SHIFT)
large_shift: In expression 1 << pool, left shifting by more than 31 bits
has undefined behavior. The shift amount, pool, is at least 32.

This patch limits mask shift to be in range of 32 bit PFVFTE[1] register,
for pool > 31.

Fixes: fe3a45fd4104 ("ixgbe: add VMDq support")

Signed-off-by: Tomasz Kulasek <tomaszx.kulasek@intel.com>
---
 drivers/net/ixgbe/ixgbe_ethdev.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Comments

Wenzhuo Lu April 18, 2016, 1:58 a.m. UTC | #1 
Hi,

> -----Original Message-----
> From: dev [mailto:dev-bounces@dpdk.org] On Behalf Of Tomasz Kulasek
> Sent: Friday, April 15, 2016 10:33 PM
> To: dev@dpdk.org
> Cc: Zhang, Helin; Ananyev, Konstantin
> Subject: [dpdk-dev] [PATCH] ixgbe: fix bad shift operation in ixgbe_set_pool_tx
> 
> CID 13190 (#1 of 1): Bad bit shift operation (BAD_SHIFT)
> large_shift: In expression 1 << pool, left shifting by more than 31 bits has
> undefined behavior. The shift amount, pool, is at least 32.
> 
> This patch limits mask shift to be in range of 32 bit PFVFTE[1] register, for pool >
> 31.
> 
> Fixes: fe3a45fd4104 ("ixgbe: add VMDq support")
> 
> Signed-off-by: Tomasz Kulasek <tomaszx.kulasek@intel.com>
Acked-by: Wenzhuo Lu <wenzhuo.lu@intel.com>
Bruce Richardson April 21, 2016, 1:53 p.m. UTC | #2 
On Mon, Apr 18, 2016 at 01:58:02AM +0000, Lu, Wenzhuo wrote:
> Hi,
> 
> > -----Original Message-----
> > From: dev [mailto:dev-bounces@dpdk.org] On Behalf Of Tomasz Kulasek
> > Sent: Friday, April 15, 2016 10:33 PM
> > To: dev@dpdk.org
> > Cc: Zhang, Helin; Ananyev, Konstantin
> > Subject: [dpdk-dev] [PATCH] ixgbe: fix bad shift operation in ixgbe_set_pool_tx
> > 
> > CID 13190 (#1 of 1): Bad bit shift operation (BAD_SHIFT)
> > large_shift: In expression 1 << pool, left shifting by more than 31 bits has
> > undefined behavior. The shift amount, pool, is at least 32.
> > 
> > This patch limits mask shift to be in range of 32 bit PFVFTE[1] register, for pool >
> > 31.
> > 
> > Fixes: fe3a45fd4104 ("ixgbe: add VMDq support")
> > 
> > Signed-off-by: Tomasz Kulasek <tomaszx.kulasek@intel.com>
> Acked-by: Wenzhuo Lu <wenzhuo.lu@intel.com>
> 
As with the rx function, I feel that this isn't the best fix, but that parameter
checking and returning an error might be better.

Also, since this is the same issue with the same fix repeated for both RX and TX
both fixes can probably be included in the same patch for a V2.

/Bruce
diff mbox

Patch

diff --git a/drivers/net/ixgbe/ixgbe_ethdev.c b/drivers/net/ixgbe/ixgbe_ethdev.c
index f676a64..6ae82e7 100644
--- a/drivers/net/ixgbe/ixgbe_ethdev.c
+++ b/drivers/net/ixgbe/ixgbe_ethdev.c
@@ -4428,7 +4428,7 @@  ixgbe_set_pool_tx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
 
 	addr = IXGBE_VFTE(pool >= ETH_64_POOLS/2);
 	reg = IXGBE_READ_REG(hw, addr);
-	val = bit1 << pool;
+	val = bit1 << (pool & 0x01F);
 
 	if (on)
 		reg |= val;