From patchwork Wed Mar 2 13:55:18 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ravi Kerur X-Patchwork-Id: 10993 Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [IPv6:::1]) by dpdk.org (Postfix) with ESMTP id 898BA9AA8; Wed, 2 Mar 2016 14:55:18 +0100 (CET) Received: from mail-pa0-f41.google.com (mail-pa0-f41.google.com [209.85.220.41]) by dpdk.org (Postfix) with ESMTP id CE0449611 for ; Wed, 2 Mar 2016 14:55:16 +0100 (CET) Received: by mail-pa0-f41.google.com with SMTP id fy10so133078273pac.1 for ; Wed, 02 Mar 2016 05:55:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id; bh=fGvo1HdroL3X03aerfeofDDfCt6OcbN/g8f+iyiR0ZY=; b=Zmhv/SYuBwlc+KQk+nTH4ZXhU4URmz2SWtoumSnR5dBsBqvCSlSyfb2o9QtmCHTUSy p17Wnxf6j2huYj0unnP72NoVNqNDYdBQnUbpi6md4e2Zydglxsp7H8tq2gdxlC5a0rJK n02W6nO6jGGtWf3kLYL368FGSNVYYOj3Grh534Mh/2sz6jb72aSgGOfTGJfcwYaVEayQ 4qEGTNajEmN1bZxrP5xdH0YP3NcXK+X3h6YHyj3rNZIUeE42TVEtxBlWYZtu37jjoyEV VVvqerCDG2SRu0KVwAja/2Ukp9PQM5hquE/KMsTy7QESAgmib69Gj3Ytc+gAxyxhEdqi 2uUA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=fGvo1HdroL3X03aerfeofDDfCt6OcbN/g8f+iyiR0ZY=; b=lP0p31Ha9OccnACehbEhfMpVF9bcaLDtFnRh5wH+o10pvsJvUWtETzD71NC/DdkO38 PP0ClGv3rYWwleW2gpvGuAxaVGGxXbkSrl/59sjOWsdQXw9IbTWVVs52qf3yRj2DzSzA LidxlQIciR3GQoYoA0nBxC924Q4HKi3VUVKgwCgw/+nMXLQyr+d/Ls1GGYFRFFGH5sQx o0z/z0eLb2G54jqgmpCrDy5ccMZtR+Gx7BFkyfDNmKlbv4X3EhtWkoMisiAY4mOOzZ5d niEESwT49bdG0arO59bgRCuDr81lyv5q+4VIcuzbmqub/zcLd6j897kNjx7Cmhy9E4IZ 2N5Q== X-Gm-Message-State: AD7BkJI7gzz3GEKYZvk/EmUh99T1FXyNraCsvAq7FMbc7VhOp3T5+Z54YbQxxk0mWSgPRw== X-Received: by 10.66.129.130 with SMTP id nw2mr38976877pab.80.1456926916103; Wed, 02 Mar 2016 05:55:16 -0800 (PST) Received: from user-PC.hsd1.ca.comcast.net (c-24-130-109-45.hsd1.ca.comcast.net. [24.130.109.45]) by smtp.gmail.com with ESMTPSA id yj1sm53465223pac.16.2016.03.02.05.55.15 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 02 Mar 2016 05:55:15 -0800 (PST) From: Ravi Kerur To: dev@dpdk.org Date: Wed, 2 Mar 2016 05:55:18 -0800 Message-Id: <1456926918-30688-1-git-send-email-rkerur@gmail.com> X-Mailer: git-send-email 1.9.1 Cc: wenzhou.lu@intel.com Subject: [dpdk-dev] [PATCH v1] I217 and I218 changes X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" v1: Make necessary changes to support I217 and I218 NICs. Use v2' incorporating internal review comments as a base. Internal review done by Wenzhou Lu (Intel) and internal review versions and testing shown below v2': Incorporate Wenzhou's comments, remove superfluous assignment to fc.requested_mode in em_hardware_init function. Compiled and tested (via testpmd) on Ubuntu 14.04 on target x86_64-native-linuxapp-gcc Compiled for target x86_64-native-linuxapp-clang v1': Modified driver and eal code to support I217 and I218 Intel NICs. Compiled and tested (via testpmd) on Ubuntu 14.04 for target x86_64-native-linuxapp-gcc Compiled for target x86_64-native-linuxapp-clang M. Jay(Intel) had used the patch for DPDK demo. Signed-off-by: Ravi Kerur Acked-by: Wenzhuo Lu --- drivers/net/e1000/base/e1000_osdep.h | 26 +++++++++++++++----- drivers/net/e1000/em_ethdev.c | 32 +++++++++++++++++++++++++ lib/librte_eal/common/include/rte_pci_dev_ids.h | 9 +++++++ 3 files changed, 61 insertions(+), 6 deletions(-) diff --git a/drivers/net/e1000/base/e1000_osdep.h b/drivers/net/e1000/base/e1000_osdep.h index b2c76e3..47a1948 100644 --- a/drivers/net/e1000/base/e1000_osdep.h +++ b/drivers/net/e1000/base/e1000_osdep.h @@ -96,21 +96,35 @@ typedef int bool; #define E1000_PCI_REG(reg) (*((volatile uint32_t *)(reg))) +#define E1000_PCI_REG16(reg) (*((volatile uint16_t *)(reg))) + #define E1000_PCI_REG_WRITE(reg, value) do { \ E1000_PCI_REG((reg)) = (rte_cpu_to_le_32(value)); \ } while (0) +#define E1000_PCI_REG_WRITE16(reg, value) do { \ + E1000_PCI_REG16((reg)) = (rte_cpu_to_le_16(value)); \ +} while (0) + #define E1000_PCI_REG_ADDR(hw, reg) \ ((volatile uint32_t *)((char *)(hw)->hw_addr + (reg))) #define E1000_PCI_REG_ARRAY_ADDR(hw, reg, index) \ E1000_PCI_REG_ADDR((hw), (reg) + ((index) << 2)) -static inline uint32_t e1000_read_addr(volatile void* addr) +#define E1000_PCI_REG_FLASH_ADDR(hw, reg) \ + ((volatile uint32_t *)((char *)(hw)->flash_address + (reg))) + +static inline uint32_t e1000_read_addr(volatile void *addr) { return rte_le_to_cpu_32(E1000_PCI_REG(addr)); } +static inline uint16_t e1000_read_addr16(volatile void *addr) +{ + return rte_le_to_cpu_16(E1000_PCI_REG16(addr)); +} + /* Necessary defines */ #define E1000_MRQC_ENABLE_MASK 0x00000007 #define E1000_MRQC_RSS_FIELD_IPV6_EX 0x00080000 @@ -155,20 +169,20 @@ static inline uint32_t e1000_read_addr(volatile void* addr) E1000_WRITE_REG(hw, reg, value) /* - * Not implemented. + * Tested on I217/I218 chipset. */ #define E1000_READ_FLASH_REG(hw, reg) \ - (E1000_ACCESS_PANIC(E1000_READ_FLASH_REG, hw, reg, 0), 0) + e1000_read_addr(E1000_PCI_REG_FLASH_ADDR((hw), (reg))) #define E1000_READ_FLASH_REG16(hw, reg) \ - (E1000_ACCESS_PANIC(E1000_READ_FLASH_REG16, hw, reg, 0), 0) + e1000_read_addr16(E1000_PCI_REG_FLASH_ADDR((hw), (reg))) #define E1000_WRITE_FLASH_REG(hw, reg, value) \ - E1000_ACCESS_PANIC(E1000_WRITE_FLASH_REG, hw, reg, value) + E1000_PCI_REG_WRITE(E1000_PCI_REG_FLASH_ADDR((hw), (reg)), (value)) #define E1000_WRITE_FLASH_REG16(hw, reg, value) \ - E1000_ACCESS_PANIC(E1000_WRITE_FLASH_REG16, hw, reg, value) + E1000_PCI_REG_WRITE16(E1000_PCI_REG_FLASH_ADDR((hw), (reg)), (value)) #define STATIC static diff --git a/drivers/net/e1000/em_ethdev.c b/drivers/net/e1000/em_ethdev.c index 4a843fe..a8c26ed 100644 --- a/drivers/net/e1000/em_ethdev.c +++ b/drivers/net/e1000/em_ethdev.c @@ -231,6 +231,32 @@ rte_em_dev_atomic_write_link_status(struct rte_eth_dev *dev, return 0; } +/** + * eth_em_dev_is_ich8 - Check for ICH8 device + * @hw: pointer to the HW structure + * + * return TRUE for ICH8, otherwise FALSE + **/ +static bool +eth_em_dev_is_ich8(struct e1000_hw *hw) +{ + DEBUGFUNC("eth_em_dev_is_ich8"); + + switch (hw->device_id) { + case E1000_DEV_ID_PCH_LPT_I217_LM: + case E1000_DEV_ID_PCH_LPT_I217_V: + case E1000_DEV_ID_PCH_LPTLP_I218_LM: + case E1000_DEV_ID_PCH_LPTLP_I218_V: + case E1000_DEV_ID_PCH_I218_V2: + case E1000_DEV_ID_PCH_I218_LM2: + case E1000_DEV_ID_PCH_I218_V3: + case E1000_DEV_ID_PCH_I218_LM3: + return 1; + default: + return 0; + } +} + static int eth_em_dev_init(struct rte_eth_dev *eth_dev) { @@ -265,6 +291,8 @@ eth_em_dev_init(struct rte_eth_dev *eth_dev) adapter->stopped = 0; /* For ICH8 support we'll need to map the flash memory BAR */ + if (eth_em_dev_is_ich8(hw)) + hw->flash_address = (void *)pci_dev->mem_resource[1].addr; if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS || em_hw_init(hw) != 0) { @@ -490,6 +518,7 @@ em_set_pba(struct e1000_hw *hw) break; case e1000_pchlan: case e1000_pch2lan: + case e1000_pch_lpt: pba = E1000_PBA_26K; break; default: @@ -798,6 +827,8 @@ em_hardware_init(struct e1000_hw *hw) hw->fc.low_water = 0x5048; hw->fc.pause_time = 0x0650; hw->fc.refresh_time = 0x0400; + } else if (hw->mac.type == e1000_pch_lpt) { + hw->fc.requested_mode = e1000_fc_full; } diag = e1000_init_hw(hw); @@ -969,6 +1000,7 @@ em_get_max_pktlen(const struct e1000_hw *hw) case e1000_ich9lan: case e1000_ich10lan: case e1000_pch2lan: + case e1000_pch_lpt: case e1000_82574: case e1000_80003es2lan: /* 9K Jumbo Frame size */ case e1000_82583: diff --git a/lib/librte_eal/common/include/rte_pci_dev_ids.h b/lib/librte_eal/common/include/rte_pci_dev_ids.h index d088191..85acaaf 100644 --- a/lib/librte_eal/common/include/rte_pci_dev_ids.h +++ b/lib/librte_eal/common/include/rte_pci_dev_ids.h @@ -310,6 +310,15 @@ RTE_PCI_DEV_ID_DECL_EM(PCI_VENDOR_ID_INTEL, E1000_DEV_ID_82573L) RTE_PCI_DEV_ID_DECL_EM(PCI_VENDOR_ID_INTEL, E1000_DEV_ID_82574L) RTE_PCI_DEV_ID_DECL_EM(PCI_VENDOR_ID_INTEL, E1000_DEV_ID_82574LA) RTE_PCI_DEV_ID_DECL_EM(PCI_VENDOR_ID_INTEL, E1000_DEV_ID_82583V) +RTE_PCI_DEV_ID_DECL_EM(PCI_VENDOR_ID_INTEL, E1000_DEV_ID_PCH_LPT_I217_LM) +RTE_PCI_DEV_ID_DECL_EM(PCI_VENDOR_ID_INTEL, E1000_DEV_ID_PCH_LPT_I217_V) +RTE_PCI_DEV_ID_DECL_EM(PCI_VENDOR_ID_INTEL, E1000_DEV_ID_PCH_LPTLP_I218_LM) +RTE_PCI_DEV_ID_DECL_EM(PCI_VENDOR_ID_INTEL, E1000_DEV_ID_PCH_LPTLP_I218_V) +RTE_PCI_DEV_ID_DECL_EM(PCI_VENDOR_ID_INTEL, E1000_DEV_ID_PCH_I218_LM2) +RTE_PCI_DEV_ID_DECL_EM(PCI_VENDOR_ID_INTEL, E1000_DEV_ID_PCH_I218_V2) +RTE_PCI_DEV_ID_DECL_EM(PCI_VENDOR_ID_INTEL, E1000_DEV_ID_PCH_I218_LM3) +RTE_PCI_DEV_ID_DECL_EM(PCI_VENDOR_ID_INTEL, E1000_DEV_ID_PCH_I218_V3) + /******************** Physical IGB devices from e1000_hw.h ********************/