From patchwork Wed Mar 2 11:29:58 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jingjing Wu X-Patchwork-Id: 10976 X-Patchwork-Delegate: bruce.richardson@intel.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [IPv6:::1]) by dpdk.org (Postfix) with ESMTP id B9C939AC2; Wed, 2 Mar 2016 12:30:25 +0100 (CET) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by dpdk.org (Postfix) with ESMTP id 3659D9AB5 for ; Wed, 2 Mar 2016 12:30:24 +0100 (CET) Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga101.fm.intel.com with ESMTP; 02 Mar 2016 03:30:23 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.22,528,1449561600"; d="scan'208";a="927860494" Received: from shvmail01.sh.intel.com ([10.239.29.42]) by fmsmga002.fm.intel.com with ESMTP; 02 Mar 2016 03:30:22 -0800 Received: from shecgisg004.sh.intel.com (shecgisg004.sh.intel.com [10.239.29.89]) by shvmail01.sh.intel.com with ESMTP id u22BUKVg028166; Wed, 2 Mar 2016 19:30:20 +0800 Received: from shecgisg004.sh.intel.com (localhost [127.0.0.1]) by shecgisg004.sh.intel.com (8.13.6/8.13.6/SuSE Linux 0.8) with ESMTP id u22BUI36031753; Wed, 2 Mar 2016 19:30:20 +0800 Received: (from wujingji@localhost) by shecgisg004.sh.intel.com (8.13.6/8.13.6/Submit) id u22BUIQm031749; Wed, 2 Mar 2016 19:30:18 +0800 From: Jingjing Wu To: bruce.richardson@intel.com Date: Wed, 2 Mar 2016 19:29:58 +0800 Message-Id: <1456918207-31696-4-git-send-email-jingjing.wu@intel.com> X-Mailer: git-send-email 1.7.4.1 In-Reply-To: <1456918207-31696-1-git-send-email-jingjing.wu@intel.com> References: <1453789575-6297-1-git-send-email-jingjing.wu@intel.com> <1456918207-31696-1-git-send-email-jingjing.wu@intel.com> Cc: dev@dpdk.org Subject: [dpdk-dev] [PATCH v2 03/12] i40e: remove flex payload from INPUT_SET_SELECT operation X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" In this patch, flex payload is removed from valid fdir input set values. It is because all flex payload configuration can be set in struct rte_fdir_conf during device configure phase. And it is a more flexible configuration including flexpayload's selection, input set selection by word and mask setting in bits. Signed-off-by: Jingjing Wu --- drivers/net/i40e/i40e_ethdev.c | 59 +++++++++++++++++++----------------------- 1 file changed, 26 insertions(+), 33 deletions(-) diff --git a/drivers/net/i40e/i40e_ethdev.c b/drivers/net/i40e/i40e_ethdev.c index 85419ab..63a1df3 100644 --- a/drivers/net/i40e/i40e_ethdev.c +++ b/drivers/net/i40e/i40e_ethdev.c @@ -262,7 +262,8 @@ #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7 0x0000000000000080ULL /* 8th word of flex payload */ #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8 0x0000000000000040ULL - +/* all 8 words flex payload */ +#define I40E_REG_INSET_FLEX_PAYLOAD_WORDS 0x0000000000003FC0ULL #define I40E_REG_INSET_MASK_DEFAULT 0x0000000000000000ULL #define I40E_TRANSLATE_INSET 0 @@ -6614,43 +6615,32 @@ i40e_get_valid_input_set(enum i40e_filter_pctype pctype, */ static const uint64_t valid_fdir_inset_table[] = { [I40E_FILTER_PCTYPE_FRAG_IPV4] = - I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST | - I40E_INSET_FLEX_PAYLOAD, + I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST, [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] = I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST | - I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT | - I40E_INSET_FLEX_PAYLOAD, + I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT, [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] = - I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST | - I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT | - I40E_INSET_FLEX_PAYLOAD, + I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST, [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] = I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST | I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT | - I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD, + I40E_INSET_SCTP_VT, [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] = - I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST | - I40E_INSET_FLEX_PAYLOAD, + I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST, [I40E_FILTER_PCTYPE_FRAG_IPV6] = - I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST | - I40E_INSET_FLEX_PAYLOAD, + I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST, [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] = - I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST | - I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT | - I40E_INSET_FLEX_PAYLOAD, + I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST, [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] = - I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST | - I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT | - I40E_INSET_FLEX_PAYLOAD, + I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST, [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] = I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT | - I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD, + I40E_INSET_SCTP_VT, [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] = - I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST | - I40E_INSET_FLEX_PAYLOAD, + I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST, [I40E_FILTER_PCTYPE_L2_PAYLOAD] = - I40E_INSET_LAST_ETHER_TYPE | I40E_INSET_FLEX_PAYLOAD, + I40E_INSET_LAST_ETHER_TYPE, }; if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD) @@ -6878,7 +6868,7 @@ i40e_translate_input_set_reg(uint64_t input) return val; } -static uint8_t +static int i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem) { uint8_t i, idx = 0; @@ -6896,16 +6886,13 @@ i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem) if (!inset || !mask || !nb_elem) return 0; - if (!inset && nb_elem >= I40E_INSET_MASK_NUM_REG) { - for (i = 0; i < I40E_INSET_MASK_NUM_REG; i++) - mask[i] = 0; - return I40E_INSET_MASK_NUM_REG; - } for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) { - if (idx >= nb_elem) - break; - if (inset & inset_mask_map[i].inset) { + if ((inset & inset_mask_map[i].inset) == inset_mask_map[i].inset) { + if (idx >= nb_elem) { + PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks"); + return -EINVAL; + } mask[idx] = inset_mask_map[i].mask; idx++; } @@ -7040,7 +7027,13 @@ i40e_fdir_filter_inset_select(struct i40e_pf *pf, inset_reg <<= I40E_32_BIT_WIDTH; inset_reg |= I40E_READ_REG(hw, I40E_PRTQF_FD_INSET(pctype, 0)); - if (conf->op == RTE_ETH_INPUT_SET_ADD) + /* Can not change the inset reg for flex payload for fdir, + * it is done by writing I40E_PRTQF_FD_FLXINSET + * in i40e_set_flex_mask_on_pctype. + */ + if (conf->op == RTE_ETH_INPUT_SET_SELECT) + inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS; + else input_set |= pf->fdir.input_set[pctype]; num = i40e_generate_inset_mask_reg(input_set, mask_reg, I40E_INSET_MASK_NUM_REG);