From patchwork Thu Feb 18 06:30:19 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Zhang, Helin" X-Patchwork-Id: 10611 Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [IPv6:::1]) by dpdk.org (Postfix) with ESMTP id 18042C446; Thu, 18 Feb 2016 07:31:33 +0100 (CET) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by dpdk.org (Postfix) with ESMTP id 4B047C440 for ; Thu, 18 Feb 2016 07:31:30 +0100 (CET) Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by orsmga102.jf.intel.com with ESMTP; 17 Feb 2016 22:31:29 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.22,464,1449561600"; d="scan'208";a="49963923" Received: from shvmail01.sh.intel.com ([10.239.29.42]) by fmsmga004.fm.intel.com with ESMTP; 17 Feb 2016 22:31:30 -0800 Received: from shecgisg004.sh.intel.com (shecgisg004.sh.intel.com [10.239.29.89]) by shvmail01.sh.intel.com with ESMTP id u1I6VRAf030968; Thu, 18 Feb 2016 14:31:27 +0800 Received: from shecgisg004.sh.intel.com (localhost [127.0.0.1]) by shecgisg004.sh.intel.com (8.13.6/8.13.6/SuSE Linux 0.8) with ESMTP id u1I6VNQT012335; Thu, 18 Feb 2016 14:31:25 +0800 Received: (from hzhan75@localhost) by shecgisg004.sh.intel.com (8.13.6/8.13.6/Submit) id u1I6VNMU012331; Thu, 18 Feb 2016 14:31:23 +0800 From: Helin Zhang To: dev@dpdk.org Date: Thu, 18 Feb 2016 14:30:19 +0800 Message-Id: <1455777020-12095-30-git-send-email-helin.zhang@intel.com> X-Mailer: git-send-email 1.7.4.1 In-Reply-To: <1455777020-12095-1-git-send-email-helin.zhang@intel.com> References: <1452825653-623-1-git-send-email-helin.zhang@intel.com> <1455777020-12095-1-git-send-email-helin.zhang@intel.com> Subject: [dpdk-dev] [PATCH v2 29/30] i40e: use rx control function for rx control registers X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" As required, rx control registers have to be read/written by rx control functions, otherwise if may fail to read/write when under stress small traffic. Signed-off-by: Helin Zhang --- drivers/net/i40e/i40e_ethdev.c | 66 ++++++++++++++++++++------------------- drivers/net/i40e/i40e_ethdev_vf.c | 28 ++++++++--------- drivers/net/i40e/i40e_fdir.c | 13 ++++---- drivers/net/i40e/i40e_pf.c | 6 ++-- 4 files changed, 58 insertions(+), 55 deletions(-) diff --git a/drivers/net/i40e/i40e_ethdev.c b/drivers/net/i40e/i40e_ethdev.c index 614bd5b..6241bfc 100644 --- a/drivers/net/i40e/i40e_ethdev.c +++ b/drivers/net/i40e/i40e_ethdev.c @@ -5632,11 +5632,11 @@ i40e_pf_disable_rss(struct i40e_pf *pf) struct i40e_hw *hw = I40E_PF_TO_HW(pf); uint64_t hena; - hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0)); - hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32; + hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0)); + hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32; hena &= ~I40E_RSS_HENA_ALL; - I40E_WRITE_REG(hw, I40E_PFQF_HENA(0), (uint32_t)hena); - I40E_WRITE_REG(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32)); + i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena); + i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32)); I40E_WRITE_FLUSH(hw); } @@ -5669,7 +5669,7 @@ i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len) uint16_t i; for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++) - I40E_WRITE_REG(hw, I40E_PFQF_HKEY(i), hash_key[i]); + i40e_write_rx_ctl(hw, I40E_PFQF_HKEY(i), hash_key[i]); I40E_WRITE_FLUSH(hw); } @@ -5698,7 +5698,7 @@ i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len) uint16_t i; for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++) - key_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HKEY(i)); + key_dw[i] = i40e_read_rx_ctl(hw, I40E_PFQF_HKEY(i)); } *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t); @@ -5719,12 +5719,12 @@ i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf) return ret; rss_hf = rss_conf->rss_hf; - hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0)); - hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32; + hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0)); + hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32; hena &= ~I40E_RSS_HENA_ALL; hena |= i40e_config_hena(rss_hf); - I40E_WRITE_REG(hw, I40E_PFQF_HENA(0), (uint32_t)hena); - I40E_WRITE_REG(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32)); + i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena); + i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32)); I40E_WRITE_FLUSH(hw); return 0; @@ -5739,8 +5739,8 @@ i40e_dev_rss_hash_update(struct rte_eth_dev *dev, uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL; uint64_t hena; - hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0)); - hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32; + hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0)); + hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32; if (!(hena & I40E_RSS_HENA_ALL)) { /* RSS disabled */ if (rss_hf != 0) /* Enable RSS */ return -EINVAL; @@ -5764,8 +5764,8 @@ i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev, i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key, &rss_conf->rss_key_len); - hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0)); - hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32; + hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0)); + hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32; rss_conf->rss_hf = i40e_parse_hena(hena); return 0; @@ -6266,7 +6266,7 @@ i40e_pf_config_mq_rx(struct i40e_pf *pf) static void i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable) { - uint32_t reg = I40E_READ_REG(hw, I40E_PRTQF_CTL_0); + uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0); *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0; } @@ -6275,7 +6275,7 @@ i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable) static void i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable) { - uint32_t reg = I40E_READ_REG(hw, I40E_PRTQF_CTL_0); + uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0); if (enable > 0) { if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) { @@ -6292,7 +6292,7 @@ i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable) } reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK; } - I40E_WRITE_REG(hw, I40E_PRTQF_CTL_0, reg); + i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg); I40E_WRITE_FLUSH(hw); } @@ -6310,7 +6310,7 @@ i40e_get_hash_filter_global_config(struct i40e_hw *hw, enum i40e_filter_pctype pctype; memset(g_cfg, 0, sizeof(*g_cfg)); - reg = I40E_READ_REG(hw, I40E_GLQF_CTL); + reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL); if (reg & I40E_GLQF_CTL_HTOEP_MASK) g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ; else @@ -6325,7 +6325,7 @@ i40e_get_hash_filter_global_config(struct i40e_hw *hw, /* Bit set indicats the coresponding flow type is supported */ g_cfg->valid_bit_mask[0] |= (1UL << i); pctype = i40e_flowtype_to_pctype(i); - reg = I40E_READ_REG(hw, I40E_GLQF_HSYM(pctype)); + reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(pctype)); if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK) g_cfg->sym_hash_enable_mask[0] |= (1UL << i); } @@ -6398,10 +6398,10 @@ i40e_set_hash_filter_global_config(struct i40e_hw *hw, pctype = i40e_flowtype_to_pctype(i); reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ? I40E_GLQF_HSYM_SYMH_ENA_MASK : 0; - I40E_WRITE_REG(hw, I40E_GLQF_HSYM(pctype), reg); + i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(pctype), reg); } - reg = I40E_READ_REG(hw, I40E_GLQF_CTL); + reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL); if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) { /* Toeplitz */ if (reg & I40E_GLQF_CTL_HTOEP_MASK) { @@ -6422,7 +6422,7 @@ i40e_set_hash_filter_global_config(struct i40e_hw *hw, /* Use the default, and keep it as it is */ goto out; - I40E_WRITE_REG(hw, I40E_GLQF_CTL, reg); + i40e_write_rx_ctl(hw, I40E_GLQF_CTL, reg); out: I40E_WRITE_FLUSH(hw); @@ -6845,13 +6845,13 @@ i40e_get_reg_inset(struct i40e_hw *hw, enum rte_filter_type filter, uint64_t reg = 0; if (filter == RTE_ETH_FILTER_HASH) { - reg = I40E_READ_REG(hw, I40E_GLQF_HASH_INSET(1, pctype)); + reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype)); reg <<= I40E_32_BIT_WIDTH; - reg |= I40E_READ_REG(hw, I40E_GLQF_HASH_INSET(0, pctype)); + reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype)); } else if (filter == RTE_ETH_FILTER_FDIR) { - reg = I40E_READ_REG(hw, I40E_PRTQF_FD_INSET(pctype, 1)); + reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1)); reg <<= I40E_32_BIT_WIDTH; - reg |= I40E_READ_REG(hw, I40E_PRTQF_FD_INSET(pctype, 0)); + reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0)); } return reg; @@ -6860,13 +6860,13 @@ i40e_get_reg_inset(struct i40e_hw *hw, enum rte_filter_type filter, static void i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val) { - uint32_t reg = I40E_READ_REG(hw, addr); + uint32_t reg = i40e_read_rx_ctl(hw, addr); PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x\n", addr, reg); if (reg != val) - I40E_WRITE_REG(hw, addr, val); + i40e_write_rx_ctl(hw, addr, val); PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x\n", addr, - (uint32_t)I40E_READ_REG(hw, addr)); + (uint32_t)i40e_read_rx_ctl(hw, addr)); } static int @@ -6895,7 +6895,8 @@ i40e_set_hash_inset_mask(struct i40e_hw *hw, uint8_t j, count = 0; for (i = 0; i < I40E_INSET_MASK_NUM_REG; i++) { - reg = I40E_READ_REG(hw, I40E_GLQF_HASH_MSK(i, pctype)); + reg = i40e_read_rx_ctl(hw, + I40E_GLQF_HASH_MSK(i, pctype)); if (reg & I40E_GLQF_HASH_MSK_MASK_MASK) count++; } @@ -6936,7 +6937,8 @@ i40e_set_fd_inset_mask(struct i40e_hw *hw, uint8_t j, count = 0; for (i = 0; i < I40E_INSET_MASK_NUM_REG; i++) { - reg = I40E_READ_REG(hw, I40E_GLQF_FD_MSK(i, pctype)); + reg = i40e_read_rx_ctl(hw, + I40E_GLQF_FD_MSK(i, pctype)); if (reg & I40E_GLQF_FD_MSK_MASK_MASK) count++; } @@ -7263,7 +7265,7 @@ static void i40e_hw_init(struct i40e_hw *hw) { /* clear the PF Queue Filter control register */ - I40E_WRITE_REG(hw, I40E_PFQF_CTL_0, 0); + i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0); /* Disable symmetric hash per port */ i40e_set_symmetric_hash_enable_per_port(hw, 0); diff --git a/drivers/net/i40e/i40e_ethdev_vf.c b/drivers/net/i40e/i40e_ethdev_vf.c index 13c5b3d..bd5c091 100644 --- a/drivers/net/i40e/i40e_ethdev_vf.c +++ b/drivers/net/i40e/i40e_ethdev_vf.c @@ -2229,7 +2229,7 @@ i40evf_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len) uint16_t i; for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++) - I40E_WRITE_REG(hw, I40E_VFQF_HKEY(i), hash_key[i]); + i40e_write_rx_ctl(hw, I40E_VFQF_HKEY(i), hash_key[i]); I40EVF_WRITE_FLUSH(hw); } @@ -2258,7 +2258,7 @@ i40evf_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len) uint16_t i; for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++) - key_dw[i] = I40E_READ_REG(hw, I40E_VFQF_HKEY(i)); + key_dw[i] = i40e_read_rx_ctl(hw, I40E_VFQF_HKEY(i)); } *key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t); @@ -2278,12 +2278,12 @@ i40evf_hw_rss_hash_set(struct i40e_vf *vf, struct rte_eth_rss_conf *rss_conf) return ret; rss_hf = rss_conf->rss_hf; - hena = (uint64_t)I40E_READ_REG(hw, I40E_VFQF_HENA(0)); - hena |= ((uint64_t)I40E_READ_REG(hw, I40E_VFQF_HENA(1))) << 32; + hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(0)); + hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(1))) << 32; hena &= ~I40E_RSS_HENA_ALL; hena |= i40e_config_hena(rss_hf); - I40E_WRITE_REG(hw, I40E_VFQF_HENA(0), (uint32_t)hena); - I40E_WRITE_REG(hw, I40E_VFQF_HENA(1), (uint32_t)(hena >> 32)); + i40e_write_rx_ctl(hw, I40E_VFQF_HENA(0), (uint32_t)hena); + i40e_write_rx_ctl(hw, I40E_VFQF_HENA(1), (uint32_t)(hena >> 32)); I40EVF_WRITE_FLUSH(hw); return 0; @@ -2295,11 +2295,11 @@ i40evf_disable_rss(struct i40e_vf *vf) struct i40e_hw *hw = I40E_VF_TO_HW(vf); uint64_t hena; - hena = (uint64_t)I40E_READ_REG(hw, I40E_VFQF_HENA(0)); - hena |= ((uint64_t)I40E_READ_REG(hw, I40E_VFQF_HENA(1))) << 32; + hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(0)); + hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(1))) << 32; hena &= ~I40E_RSS_HENA_ALL; - I40E_WRITE_REG(hw, I40E_VFQF_HENA(0), (uint32_t)hena); - I40E_WRITE_REG(hw, I40E_VFQF_HENA(1), (uint32_t)(hena >> 32)); + i40e_write_rx_ctl(hw, I40E_VFQF_HENA(0), (uint32_t)hena); + i40e_write_rx_ctl(hw, I40E_VFQF_HENA(1), (uint32_t)(hena >> 32)); I40EVF_WRITE_FLUSH(hw); } @@ -2356,8 +2356,8 @@ i40evf_dev_rss_hash_update(struct rte_eth_dev *dev, uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL; uint64_t hena; - hena = (uint64_t)I40E_READ_REG(hw, I40E_VFQF_HENA(0)); - hena |= ((uint64_t)I40E_READ_REG(hw, I40E_VFQF_HENA(1))) << 32; + hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(0)); + hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(1))) << 32; if (!(hena & I40E_RSS_HENA_ALL)) { /* RSS disabled */ if (rss_hf != 0) /* Enable RSS */ return -EINVAL; @@ -2382,8 +2382,8 @@ i40evf_dev_rss_hash_conf_get(struct rte_eth_dev *dev, i40evf_get_rss_key(&vf->vsi, rss_conf->rss_key, &rss_conf->rss_key_len); - hena = (uint64_t)I40E_READ_REG(hw, I40E_VFQF_HENA(0)); - hena |= ((uint64_t)I40E_READ_REG(hw, I40E_VFQF_HENA(1))) << 32; + hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(0)); + hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(1))) << 32; rss_conf->rss_hf = i40e_parse_hena(hena); return 0; diff --git a/drivers/net/i40e/i40e_fdir.c b/drivers/net/i40e/i40e_fdir.c index 9ad6981..14c51ce 100644 --- a/drivers/net/i40e/i40e_fdir.c +++ b/drivers/net/i40e/i40e_fdir.c @@ -52,6 +52,7 @@ #include "i40e_logs.h" #include "base/i40e_type.h" +#include "base/i40e_prototype.h" #include "i40e_ethdev.h" #include "i40e_rxtx.h" @@ -369,11 +370,11 @@ i40e_init_flx_pld(struct i40e_pf *pf) if (!I40E_VALID_PCTYPE((enum i40e_filter_pctype)pctype)) continue; pf->fdir.flex_mask[pctype].word_mask = 0; - I40E_WRITE_REG(hw, I40E_PRTQF_FD_FLXINSET(pctype), 0); + i40e_write_rx_ctl(hw, I40E_PRTQF_FD_FLXINSET(pctype), 0); for (i = 0; i < I40E_FDIR_BITMASK_NUM_WORD; i++) { pf->fdir.flex_mask[pctype].bitmask[i].offset = 0; pf->fdir.flex_mask[pctype].bitmask[i].mask = 0; - I40E_WRITE_REG(hw, I40E_PRTQF_FD_MSK(pctype, i), 0); + i40e_write_rx_ctl(hw, I40E_PRTQF_FD_MSK(pctype, i), 0); } } } @@ -618,7 +619,7 @@ i40e_set_flex_mask_on_pctype(struct i40e_pf *pf, flxinset = (flex_mask->word_mask << I40E_PRTQF_FD_FLXINSET_INSET_SHIFT) & I40E_PRTQF_FD_FLXINSET_INSET_MASK; - I40E_WRITE_REG(hw, I40E_PRTQF_FD_FLXINSET(pctype), flxinset); + i40e_write_rx_ctl(hw, I40E_PRTQF_FD_FLXINSET(pctype), flxinset); for (i = 0; i < nb_bitmask; i++) { fd_mask = (flex_mask->bitmask[i].mask << @@ -628,7 +629,7 @@ i40e_set_flex_mask_on_pctype(struct i40e_pf *pf, I40E_FLX_OFFSET_IN_FIELD_VECTOR) << I40E_PRTQF_FD_MSK_OFFSET_SHIFT) & I40E_PRTQF_FD_MSK_OFFSET_MASK; - I40E_WRITE_REG(hw, I40E_PRTQF_FD_MSK(pctype, i), fd_mask); + i40e_write_rx_ctl(hw, I40E_PRTQF_FD_MSK(pctype, i), fd_mask); } } @@ -660,9 +661,9 @@ i40e_fdir_configure(struct rte_eth_dev *dev) } /* enable FDIR filter */ - val = I40E_READ_REG(hw, I40E_PFQF_CTL_0); + val = i40e_read_rx_ctl(hw, I40E_PFQF_CTL_0); val |= I40E_PFQF_CTL_0_FD_ENA_MASK; - I40E_WRITE_REG(hw, I40E_PFQF_CTL_0, val); + i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, val); i40e_init_flx_pld(pf); /* set flex config to default value */ diff --git a/drivers/net/i40e/i40e_pf.c b/drivers/net/i40e/i40e_pf.c index cbf4e5b..51ae1e7 100644 --- a/drivers/net/i40e/i40e_pf.c +++ b/drivers/net/i40e/i40e_pf.c @@ -82,8 +82,8 @@ i40e_pf_vf_queues_mapping(struct i40e_pf_vf *vf) * VF should use scatter range queues. So, it needn't * to set QBASE in this register. */ - I40E_WRITE_REG(hw, I40E_VSILAN_QBASE(vsi_id), - I40E_VSILAN_QBASE_VSIQTABLE_ENA_MASK); + i40e_write_rx_ctl(hw, I40E_VSILAN_QBASE(vsi_id), + I40E_VSILAN_QBASE_VSIQTABLE_ENA_MASK); /* Set to enable VFLAN_QTABLE[] registers valid */ I40E_WRITE_REG(hw, I40E_VPLAN_MAPENA(vf_id), @@ -108,7 +108,7 @@ i40e_pf_vf_queues_mapping(struct i40e_pf_vf *vf) q2 = qbase + 2 * i + 1; val = (q2 << I40E_VSILAN_QTABLE_QINDEX_1_SHIFT) + q1; - I40E_WRITE_REG(hw, I40E_VSILAN_QTABLE(i, vsi_id), val); + i40e_write_rx_ctl(hw, I40E_VSILAN_QTABLE(i, vsi_id), val); } I40E_WRITE_FLUSH(hw);