[dpdk-dev,v8,2/4] ethdev: Fill speed capability bitmaps in the PMDs
Commit Message
Added speed capabilities to all pmds supporting physical NICs:
* e1000
* ixgbe
* i40
* bnx2x
* cxgbe
* mlx4
* mlx5
* nfp
* fm10k
Signed-off-by: Marc Sune <marcdevel@gmail.com>
---
drivers/net/bnx2x/bnx2x_ethdev.c | 1 +
drivers/net/cxgbe/cxgbe_ethdev.c | 1 +
drivers/net/e1000/em_ethdev.c | 6 ++++++
drivers/net/e1000/igb_ethdev.c | 6 ++++++
drivers/net/fm10k/fm10k_ethdev.c | 4 ++++
drivers/net/i40e/i40e_ethdev.c | 9 +++++++++
drivers/net/ixgbe/ixgbe_ethdev.c | 10 ++++++++++
drivers/net/mlx4/mlx4.c | 4 ++++
drivers/net/mlx5/mlx5_ethdev.c | 5 +++++
drivers/net/nfp/nfp_net.c | 2 ++
10 files changed, 48 insertions(+)
Comments
On Sun, Feb 14, 2016 at 11:17:37PM +0100, Marc Sune wrote:
> Added speed capabilities to all pmds supporting physical NICs:
>
> * e1000
> * ixgbe
> * i40
> * bnx2x
> * cxgbe
> * mlx4
> * mlx5
> * nfp
> * fm10k
>[...]
> diff --git a/drivers/net/mlx5/mlx5_ethdev.c b/drivers/net/mlx5/mlx5_ethdev.c
> index 1159fa3..99dac09 100644
> --- a/drivers/net/mlx5/mlx5_ethdev.c
> +++ b/drivers/net/mlx5/mlx5_ethdev.c
> @@ -523,6 +523,11 @@ mlx5_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *info)
> * size if it is not fixed.
> * The API should be updated to solve this problem. */
> info->reta_size = priv->ind_table_max_size;
> +
> + info->speed_capa = ETH_SPEED_CAP_1G | ETH_SPEED_CAP_10G |
> + ETH_SPEED_CAP_10G | ETH_SPEED_CAP_40G |
> + ETH_SPEED_CAP_56G;
> +
> priv_unlock(priv);
> }
Hi Marc,
I have a question about this information, is it a list of the
capabilities of the family or the capability of the NIC?
Because with ConnectX4 family we have a range of NICs which does not
support all this kind of speeds.
The speeds above are not completed the range is 1/10/25/40/50/100G.
Hi, Marc,
Best Regards,
Mark
> -----Original Message-----
> From: Nélio Laranjeiro [mailto:nelio.laranjeiro@6wind.com]
> Sent: Monday, February 15, 2016 4:43 PM
> To: Marc Sune
> Cc: dev@dpdk.org; Lu, Wenzhuo; Zhang, Helin; Harish Patil; Chen, Jing D
> Subject: Re: [dpdk-dev] [PATCH v8 2/4] ethdev: Fill speed capability bitmaps
> in the PMDs
>
> On Sun, Feb 14, 2016 at 11:17:37PM +0100, Marc Sune wrote:
> > Added speed capabilities to all pmds supporting physical NICs:
> >
> > * e1000
> > * ixgbe
> > * i40
> > * bnx2x
> > * cxgbe
> > * mlx4
> > * mlx5
> > * nfp
> > * fm10k
> >[...]
> > diff --git a/drivers/net/mlx5/mlx5_ethdev.c
> b/drivers/net/mlx5/mlx5_ethdev.c
> > index 1159fa3..99dac09 100644
> > --- a/drivers/net/mlx5/mlx5_ethdev.c
> > +++ b/drivers/net/mlx5/mlx5_ethdev.c
> > @@ -523,6 +523,11 @@ mlx5_dev_infos_get(struct rte_eth_dev *dev,
> struct rte_eth_dev_info *info)
> > * size if it is not fixed.
> > * The API should be updated to solve this problem. */
> > info->reta_size = priv->ind_table_max_size;
> > +
> > + info->speed_capa = ETH_SPEED_CAP_1G | ETH_SPEED_CAP_10G |
> > + ETH_SPEED_CAP_10G |
> ETH_SPEED_CAP_40G |
> > + ETH_SPEED_CAP_56G;
> > +
> > priv_unlock(priv);
> > }
>
> Hi Marc,
>
> I have a question about this information, is it a list of the
> capabilities of the family or the capability of the NIC?
> Because with ConnectX4 family we have a range of NICs which does not
> support all this kind of speeds.
>
> The speeds above are not completed the range is 1/10/25/40/50/100G.
>
Fm10k also includes several cards and different ones are designed to have different speed.
A better solution for fm10k is to acquire NIC type (like, BR card for 100G/40G, Atwood for 25/10G, etc)
Then, return proper speed.
> --
> Nélio Laranjeiro
> 6WIND
Hi Marc,
On Sunday, February 02/14/16, 2016 at 23:17:37 +0100, Marc Sune wrote:
> Added speed capabilities to all pmds supporting physical NICs:
>
> * e1000
> * ixgbe
> * i40
> * bnx2x
> * cxgbe
> * mlx4
> * mlx5
> * nfp
> * fm10k
>
> Signed-off-by: Marc Sune <marcdevel@gmail.com>
> ---
> drivers/net/bnx2x/bnx2x_ethdev.c | 1 +
> drivers/net/cxgbe/cxgbe_ethdev.c | 1 +
> drivers/net/e1000/em_ethdev.c | 6 ++++++
> drivers/net/e1000/igb_ethdev.c | 6 ++++++
> drivers/net/fm10k/fm10k_ethdev.c | 4 ++++
> drivers/net/i40e/i40e_ethdev.c | 9 +++++++++
> drivers/net/ixgbe/ixgbe_ethdev.c | 10 ++++++++++
> drivers/net/mlx4/mlx4.c | 4 ++++
> drivers/net/mlx5/mlx5_ethdev.c | 5 +++++
> drivers/net/nfp/nfp_net.c | 2 ++
> 10 files changed, 48 insertions(+)
>
[...]
> diff --git a/drivers/net/cxgbe/cxgbe_ethdev.c b/drivers/net/cxgbe/cxgbe_ethdev.c
> index 97ef152..203e119 100644
> --- a/drivers/net/cxgbe/cxgbe_ethdev.c
> +++ b/drivers/net/cxgbe/cxgbe_ethdev.c
> @@ -171,6 +171,7 @@ static void cxgbe_dev_info_get(struct rte_eth_dev *eth_dev,
>
> device_info->rx_desc_lim = cxgbe_desc_lim;
> device_info->tx_desc_lim = cxgbe_desc_lim;
> + device_info->speed_capa = ETH_SPEED_CAP_10G | ETH_SPEED_CAP_40G;
> }
>
Not all Chelsio NICs support _both_ 10G and 40G speed capabilities on a
single card. You can query pi->link_cfg.supported to get the supported
speeds. Check out print_port_info() in cxgbe_main.c to help you fill
in your speed capabilities for Chelsio NICs.
Thanks,
Rahul
Rahul, Neilo, Jing D, et al
On 15 February 2016 at 15:43, Rahul Lakkireddy <rahul.lakkireddy@chelsio.com
> wrote:
> Hi Marc,
>
> On Sunday, February 02/14/16, 2016 at 23:17:37 +0100, Marc Sune wrote:
> > Added speed capabilities to all pmds supporting physical NICs:
> >
> > * e1000
> > * ixgbe
> > * i40
> > * bnx2x
> > * cxgbe
> > * mlx4
> > * mlx5
> > * nfp
> > * fm10k
> >
> > Signed-off-by: Marc Sune <marcdevel@gmail.com>
> > ---
> > drivers/net/bnx2x/bnx2x_ethdev.c | 1 +
> > drivers/net/cxgbe/cxgbe_ethdev.c | 1 +
> > drivers/net/e1000/em_ethdev.c | 6 ++++++
> > drivers/net/e1000/igb_ethdev.c | 6 ++++++
> > drivers/net/fm10k/fm10k_ethdev.c | 4 ++++
> > drivers/net/i40e/i40e_ethdev.c | 9 +++++++++
> > drivers/net/ixgbe/ixgbe_ethdev.c | 10 ++++++++++
> > drivers/net/mlx4/mlx4.c | 4 ++++
> > drivers/net/mlx5/mlx5_ethdev.c | 5 +++++
> > drivers/net/nfp/nfp_net.c | 2 ++
> > 10 files changed, 48 insertions(+)
> >
>
> [...]
>
> > diff --git a/drivers/net/cxgbe/cxgbe_ethdev.c
> b/drivers/net/cxgbe/cxgbe_ethdev.c
> > index 97ef152..203e119 100644
> > --- a/drivers/net/cxgbe/cxgbe_ethdev.c
> > +++ b/drivers/net/cxgbe/cxgbe_ethdev.c
> > @@ -171,6 +171,7 @@ static void cxgbe_dev_info_get(struct rte_eth_dev
> *eth_dev,
> >
> > device_info->rx_desc_lim = cxgbe_desc_lim;
> > device_info->tx_desc_lim = cxgbe_desc_lim;
> > + device_info->speed_capa = ETH_SPEED_CAP_10G | ETH_SPEED_CAP_40G;
> > }
> >
>
> Not all Chelsio NICs support _both_ 10G and 40G speed capabilities on a
> single card. You can query pi->link_cfg.supported to get the supported
> speeds. Check out print_port_info() in cxgbe_main.c to help you fill
> in your speed capabilities for Chelsio NICs.
>
This patch series has been long delayed, and I've been requested to merge
it for next release if possible. Most of the feedback has been coming late
(not for cxgbe, which is introduced in this new v8, but it did for most of
the rest of drivers).
My proposal is simply to add in this patch series ALL possible speeds for
that driver. Other patches can be later submitted to adjust speeds
according to specific device model.
marc
>
> Thanks,
> Rahul
>
Hi Marc,
On Mon, Feb 15, 2016 at 06:14:42PM +0100, Marc wrote:
> Rahul, Neilo, Jing D, et al
>
> On 15 February 2016 at 15:43, Rahul Lakkireddy <rahul.lakkireddy@chelsio.com
> > wrote:
>
> > Hi Marc,
> >
> > On Sunday, February 02/14/16, 2016 at 23:17:37 +0100, Marc Sune wrote:
> > > Added speed capabilities to all pmds supporting physical NICs:
> > >
> > > * e1000
> > > * ixgbe
> > > * i40
> > > * bnx2x
> > > * cxgbe
> > > * mlx4
> > > * mlx5
> > > * nfp
> > > * fm10k
> > >
> > > Signed-off-by: Marc Sune <marcdevel@gmail.com>
> > > ---
> > > drivers/net/bnx2x/bnx2x_ethdev.c | 1 +
> > > drivers/net/cxgbe/cxgbe_ethdev.c | 1 +
> > > drivers/net/e1000/em_ethdev.c | 6 ++++++
> > > drivers/net/e1000/igb_ethdev.c | 6 ++++++
> > > drivers/net/fm10k/fm10k_ethdev.c | 4 ++++
> > > drivers/net/i40e/i40e_ethdev.c | 9 +++++++++
> > > drivers/net/ixgbe/ixgbe_ethdev.c | 10 ++++++++++
> > > drivers/net/mlx4/mlx4.c | 4 ++++
> > > drivers/net/mlx5/mlx5_ethdev.c | 5 +++++
> > > drivers/net/nfp/nfp_net.c | 2 ++
> > > 10 files changed, 48 insertions(+)
> > >
> >
> > [...]
> >
> > > diff --git a/drivers/net/cxgbe/cxgbe_ethdev.c
> > b/drivers/net/cxgbe/cxgbe_ethdev.c
> > > index 97ef152..203e119 100644
> > > --- a/drivers/net/cxgbe/cxgbe_ethdev.c
> > > +++ b/drivers/net/cxgbe/cxgbe_ethdev.c
> > > @@ -171,6 +171,7 @@ static void cxgbe_dev_info_get(struct rte_eth_dev
> > *eth_dev,
> > >
> > > device_info->rx_desc_lim = cxgbe_desc_lim;
> > > device_info->tx_desc_lim = cxgbe_desc_lim;
> > > + device_info->speed_capa = ETH_SPEED_CAP_10G | ETH_SPEED_CAP_40G;
> > > }
> > >
> >
> > Not all Chelsio NICs support _both_ 10G and 40G speed capabilities on a
> > single card. You can query pi->link_cfg.supported to get the supported
> > speeds. Check out print_port_info() in cxgbe_main.c to help you fill
> > in your speed capabilities for Chelsio NICs.
> >
>
> This patch series has been long delayed, and I've been requested to merge
> it for next release if possible. Most of the feedback has been coming late
> (not for cxgbe, which is introduced in this new v8, but it did for most of
> the rest of drivers).
>
> My proposal is simply to add in this patch series ALL possible speeds for
> that driver. Other patches can be later submitted to adjust speeds
> according to specific device model.
I agree with this. I was asking in order to understand what your were
expecting from this API, for me it is clear.
You should just maintain the current situation i.e.
rte_eth_link.link_speed. This is already what your patches do.
For the link speed capability (aka device_info->speed_capa), you should
add a new line "speed capability" in the doc/guides/nics/overview.rst.
Those who think it is useful will implement it in their PMD.
Regards,
On 16 February 2016 at 16:25, Nélio Laranjeiro <nelio.laranjeiro@6wind.com>
wrote:
> Hi Marc,
>
> On Mon, Feb 15, 2016 at 06:14:42PM +0100, Marc wrote:
> > Rahul, Neilo, Jing D, et al
> >
> > On 15 February 2016 at 15:43, Rahul Lakkireddy <
> rahul.lakkireddy@chelsio.com
> > > wrote:
> >
> > > Hi Marc,
> > >
> > > On Sunday, February 02/14/16, 2016 at 23:17:37 +0100, Marc Sune wrote:
> > > > Added speed capabilities to all pmds supporting physical NICs:
> > > >
> > > > * e1000
> > > > * ixgbe
> > > > * i40
> > > > * bnx2x
> > > > * cxgbe
> > > > * mlx4
> > > > * mlx5
> > > > * nfp
> > > > * fm10k
> > > >
> > > > Signed-off-by: Marc Sune <marcdevel@gmail.com>
> > > > ---
> > > > drivers/net/bnx2x/bnx2x_ethdev.c | 1 +
> > > > drivers/net/cxgbe/cxgbe_ethdev.c | 1 +
> > > > drivers/net/e1000/em_ethdev.c | 6 ++++++
> > > > drivers/net/e1000/igb_ethdev.c | 6 ++++++
> > > > drivers/net/fm10k/fm10k_ethdev.c | 4 ++++
> > > > drivers/net/i40e/i40e_ethdev.c | 9 +++++++++
> > > > drivers/net/ixgbe/ixgbe_ethdev.c | 10 ++++++++++
> > > > drivers/net/mlx4/mlx4.c | 4 ++++
> > > > drivers/net/mlx5/mlx5_ethdev.c | 5 +++++
> > > > drivers/net/nfp/nfp_net.c | 2 ++
> > > > 10 files changed, 48 insertions(+)
> > > >
> > >
> > > [...]
> > >
> > > > diff --git a/drivers/net/cxgbe/cxgbe_ethdev.c
> > > b/drivers/net/cxgbe/cxgbe_ethdev.c
> > > > index 97ef152..203e119 100644
> > > > --- a/drivers/net/cxgbe/cxgbe_ethdev.c
> > > > +++ b/drivers/net/cxgbe/cxgbe_ethdev.c
> > > > @@ -171,6 +171,7 @@ static void cxgbe_dev_info_get(struct rte_eth_dev
> > > *eth_dev,
> > > >
> > > > device_info->rx_desc_lim = cxgbe_desc_lim;
> > > > device_info->tx_desc_lim = cxgbe_desc_lim;
> > > > + device_info->speed_capa = ETH_SPEED_CAP_10G |
> ETH_SPEED_CAP_40G;
> > > > }
> > > >
> > >
> > > Not all Chelsio NICs support _both_ 10G and 40G speed capabilities on a
> > > single card. You can query pi->link_cfg.supported to get the supported
> > > speeds. Check out print_port_info() in cxgbe_main.c to help you fill
> > > in your speed capabilities for Chelsio NICs.
> > >
> >
> > This patch series has been long delayed, and I've been requested to merge
> > it for next release if possible. Most of the feedback has been coming
> late
> > (not for cxgbe, which is introduced in this new v8, but it did for most
> of
> > the rest of drivers).
> >
> > My proposal is simply to add in this patch series ALL possible speeds for
> > that driver. Other patches can be later submitted to adjust speeds
> > according to specific device model.
>
> I agree with this. I was asking in order to understand what your were
> expecting from this API, for me it is clear.
>
> You should just maintain the current situation i.e.
> rte_eth_link.link_speed. This is already what your patches do.
>
> For the link speed capability (aka device_info->speed_capa), you should
> add a new line "speed capability" in the doc/guides/nics/overview.rst.
> Those who think it is useful will implement it in their PMD.
>
Noted for v9.
marc
>
> Regards,
>
> --
> Nélio Laranjeiro
> 6WIND
>
@@ -347,6 +347,7 @@ bnx2x_dev_infos_get(struct rte_eth_dev *dev, __rte_unused struct rte_eth_dev_inf
dev_info->min_rx_bufsize = BNX2X_MIN_RX_BUF_SIZE;
dev_info->max_rx_pktlen = BNX2X_MAX_RX_PKT_LEN;
dev_info->max_mac_addrs = BNX2X_MAX_MAC_ADDRS;
+ dev_info->speed_capa = ETH_SPEED_CAP_10G | ETH_SPEED_CAP_20G;
}
static void
@@ -171,6 +171,7 @@ static void cxgbe_dev_info_get(struct rte_eth_dev *eth_dev,
device_info->rx_desc_lim = cxgbe_desc_lim;
device_info->tx_desc_lim = cxgbe_desc_lim;
+ device_info->speed_capa = ETH_SPEED_CAP_10G | ETH_SPEED_CAP_40G;
}
static void cxgbe_dev_promiscuous_enable(struct rte_eth_dev *eth_dev)
@@ -1023,6 +1023,12 @@ eth_em_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
.nb_min = E1000_MIN_RING_DESC,
.nb_align = EM_TXD_ALIGN,
};
+
+ dev_info->speed_capa = ETH_SPEED_CAP_10M_HD |
+ ETH_SPEED_CAP_10M_FD |
+ ETH_SPEED_CAP_100M_HD |
+ ETH_SPEED_CAP_100M_FD |
+ ETH_SPEED_CAP_1G;
}
/* return 0 means link status changed, -1 means not changed */
@@ -1908,6 +1908,12 @@ eth_igb_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
dev_info->rx_desc_lim = rx_desc_lim;
dev_info->tx_desc_lim = tx_desc_lim;
+
+ dev_info->speed_capa = ETH_SPEED_CAP_10M_HD |
+ ETH_SPEED_CAP_10M_FD |
+ ETH_SPEED_CAP_100M_HD |
+ ETH_SPEED_CAP_100M_FD |
+ ETH_SPEED_CAP_1G;
}
static void
@@ -1333,6 +1333,10 @@ fm10k_dev_infos_get(struct rte_eth_dev *dev,
.nb_min = FM10K_MIN_TX_DESC,
.nb_align = FM10K_MULT_TX_DESC,
};
+
+ dev_info->speed_capa = ETH_SPEED_CAP_1G | ETH_SPEED_CAP_2_5G |
+ ETH_SPEED_CAP_10G | ETH_SPEED_CAP_25G |
+ ETH_SPEED_CAP_40G | ETH_SPEED_CAP_100G;
}
static int
@@ -2233,6 +2233,7 @@ static void
i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
{
struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
+ struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
struct i40e_vsi *vsi = pf->main_vsi;
dev_info->max_rx_queues = vsi->nb_qps;
@@ -2304,6 +2305,14 @@ i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
dev_info->max_rx_queues += dev_info->vmdq_queue_num;
dev_info->max_tx_queues += dev_info->vmdq_queue_num;
}
+
+ if (i40e_is_40G_device(hw->device_id))
+ /* For XL710 */
+ dev_info->speed_capa = ETH_SPEED_CAP_1G | ETH_SPEED_CAP_10G;
+ else
+ /* For X710 */
+ dev_info->speed_capa = ETH_SPEED_CAP_10G | ETH_SPEED_CAP_40G;
+
}
static int
@@ -2827,6 +2827,16 @@ ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
+
+ dev_info->speed_capa = ETH_SPEED_CAP_1G | ETH_SPEED_CAP_10G;
+
+ if (hw->mac.type == ixgbe_mac_X540 ||
+ hw->mac.type == ixgbe_mac_X540_vf ||
+ hw->mac.type == ixgbe_mac_X550 ||
+ hw->mac.type == ixgbe_mac_X550_vf)
+
+ dev_info->speed_capa |= ETH_SPEED_CAP_100M_FD /*|
+ ETH_SPEED_CAP_100M_HD*/;
}
static void
@@ -4264,6 +4264,10 @@ mlx4_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *info)
0);
if (priv_get_ifname(priv, &ifname) == 0)
info->if_index = if_nametoindex(ifname);
+
+ info->speed_capa = ETH_SPEED_CAP_10G |ETH_SPEED_CAP_40G |
+ ETH_SPEED_CAP_56G;
+
priv_unlock(priv);
}
@@ -523,6 +523,11 @@ mlx5_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *info)
* size if it is not fixed.
* The API should be updated to solve this problem. */
info->reta_size = priv->ind_table_max_size;
+
+ info->speed_capa = ETH_SPEED_CAP_1G | ETH_SPEED_CAP_10G |
+ ETH_SPEED_CAP_10G | ETH_SPEED_CAP_40G |
+ ETH_SPEED_CAP_56G;
+
priv_unlock(priv);
}
@@ -1071,6 +1071,8 @@ nfp_net_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
dev_info->reta_size = NFP_NET_CFG_RSS_ITBL_SZ;
dev_info->hash_key_size = NFP_NET_CFG_RSS_KEY_SZ;
+
+ dev_info->speed_capa = ETH_SPEED_CAP_50G | ETH_SPEED_CAP_100G;
}
static uint32_t