diff mbox

[dpdk-dev,2/4] szedata2: add functions for setting link up/down and updating link info

Message ID 1454019829-5908-2-git-send-email-vido@cesnet.cz (mailing list archive)
State Accepted, archived
Delegated to: Bruce Richardson
Headers show

Commit Message

Matej Vido Jan. 28, 2016, 10:23 p.m. UTC
Mmap PCI resource file and add inline functions for reading from and
writing to PCI resource address space.
Add description of IBUF and OBUF address space.
Add configuration option for setting which firmware type will be used.
Right address space values for IBUFs and OBUFs offsets are used
according to configuration option CONFIG_RTE_LIBRTE_PMD_SZEDATA2_AS.
Setting link up/down and getting info about link status is done through
mmapped PCI resource address space.

Signed-off-by: Matej Vido <vido@cesnet.cz>
---
 config/common_linuxapp                  |   11 +
 drivers/net/szedata2/rte_eth_szedata2.c |  152 +++++++++++++--
 drivers/net/szedata2/rte_eth_szedata2.h |  315 ++++++++++++++++++++++++++++++-
 3 files changed, 462 insertions(+), 16 deletions(-)
diff mbox

Patch

diff --git a/config/common_linuxapp b/config/common_linuxapp
index 74bc515..43a795c 100644
--- a/config/common_linuxapp
+++ b/config/common_linuxapp
@@ -264,6 +264,17 @@  CONFIG_RTE_LIBRTE_NFP_DEBUG=n
 # Compile software PMD backed by SZEDATA2 device
 #
 CONFIG_RTE_LIBRTE_PMD_SZEDATA2=n
+##
+## Defines firmware type address space.
+## RTE_LIBRTE_PMD_SZEDATA2_AS can be:
+## 0 - for firmwares:
+##         NIC_100G1_LR4
+##         HANIC_100G1_LR4
+##         HANIC_100G1_SR10
+##
+## Other values raise compile time error
+##
+CONFIG_RTE_LIBRTE_PMD_SZEDATA2_AS=0
 
 #
 # Compile burst-oriented VIRTIO PMD driver
diff --git a/drivers/net/szedata2/rte_eth_szedata2.c b/drivers/net/szedata2/rte_eth_szedata2.c
index ef906f3..d8c260b 100644
--- a/drivers/net/szedata2/rte_eth_szedata2.c
+++ b/drivers/net/szedata2/rte_eth_szedata2.c
@@ -1,7 +1,7 @@ 
 /*-
  *   BSD LICENSE
  *
- *   Copyright (c) 2015 CESNET
+ *   Copyright (c) 2015 - 2016 CESNET
  *   All rights reserved.
  *
  *   Redistribution and use in source and binary forms, with or without
@@ -37,6 +37,9 @@ 
 #include <err.h>
 #include <sys/types.h>
 #include <dirent.h>
+#include <sys/stat.h>
+#include <fcntl.h>
+#include <sys/mman.h>
 
 #include <libsze2.h>
 
@@ -46,6 +49,7 @@ 
 #include <rte_memcpy.h>
 #include <rte_kvargs.h>
 #include <rte_dev.h>
+#include <rte_atomic.h>
 
 #include "rte_eth_szedata2.h"
 
@@ -92,11 +96,6 @@  struct pmd_internals {
 static struct ether_addr eth_addr = {
 	.addr_bytes = { 0x00, 0x11, 0x17, 0x00, 0x00, 0x00 }
 };
-static struct rte_eth_link pmd_link = {
-		.link_speed = ETH_LINK_SPEED_10G,
-		.link_duplex = ETH_LINK_FULL_DUPLEX,
-		.link_status = 0
-};
 
 static uint16_t
 eth_szedata2_rx(void *queue,
@@ -987,7 +986,6 @@  eth_dev_start(struct rte_eth_dev *dev)
 			goto err_tx;
 	}
 
-	dev->data->dev_link.link_status = 1;
 	return 0;
 
 err_tx:
@@ -1011,8 +1009,6 @@  eth_dev_stop(struct rte_eth_dev *dev)
 
 	for (i = 0; i < nb_rx; i++)
 		eth_rx_queue_stop(dev, i);
-
-	dev->data->dev_link.link_status = 0;
 }
 
 static int
@@ -1141,9 +1137,76 @@  eth_dev_close(struct rte_eth_dev *dev)
 }
 
 static int
-eth_link_update(struct rte_eth_dev *dev __rte_unused,
+eth_link_update(struct rte_eth_dev *dev,
 		int wait_to_complete __rte_unused)
 {
+	struct rte_eth_link link;
+	struct rte_eth_link *link_ptr = &link;
+	struct rte_eth_link *dev_link = &dev->data->dev_link;
+	volatile struct szedata2_cgmii_ibuf *ibuf = SZEDATA2_PCI_RESOURCE_PTR(
+			dev, SZEDATA2_CGMII_IBUF_BASE_OFF,
+			volatile struct szedata2_cgmii_ibuf *);
+
+	switch (cgmii_link_speed(ibuf)) {
+	case SZEDATA2_LINK_SPEED_10G:
+		link.link_speed = ETH_LINK_SPEED_10G;
+		break;
+	case SZEDATA2_LINK_SPEED_40G:
+		link.link_speed = ETH_LINK_SPEED_40G;
+		break;
+	case SZEDATA2_LINK_SPEED_100G:
+		/*
+		 * TODO
+		 * If link_speed value from rte_eth_link structure
+		 * will be changed to support 100Gbps speed change
+		 * this value to 100G.
+		 */
+		link.link_speed = ETH_LINK_SPEED_10G;
+		break;
+	default:
+		link.link_speed = ETH_LINK_SPEED_10G;
+		break;
+	}
+
+	/* szedata2 uses only full duplex */
+	link.link_duplex = ETH_LINK_FULL_DUPLEX;
+
+	link.link_status = (cgmii_ibuf_is_enabled(ibuf) &&
+			cgmii_ibuf_is_link_up(ibuf)) ? 1 : 0;
+
+	rte_atomic64_cmpset((uint64_t *)dev_link, *(uint64_t *)dev_link,
+			*(uint64_t *)link_ptr);
+
+	return 0;
+}
+
+static int
+eth_dev_set_link_up(struct rte_eth_dev *dev)
+{
+	volatile struct szedata2_cgmii_ibuf *ibuf = SZEDATA2_PCI_RESOURCE_PTR(
+			dev, SZEDATA2_CGMII_IBUF_BASE_OFF,
+			volatile struct szedata2_cgmii_ibuf *);
+	volatile struct szedata2_cgmii_obuf *obuf = SZEDATA2_PCI_RESOURCE_PTR(
+			dev, SZEDATA2_CGMII_OBUF_BASE_OFF,
+			volatile struct szedata2_cgmii_obuf *);
+
+	cgmii_ibuf_enable(ibuf);
+	cgmii_obuf_enable(obuf);
+	return 0;
+}
+
+static int
+eth_dev_set_link_down(struct rte_eth_dev *dev)
+{
+	volatile struct szedata2_cgmii_ibuf *ibuf = SZEDATA2_PCI_RESOURCE_PTR(
+			dev, SZEDATA2_CGMII_IBUF_BASE_OFF,
+			volatile struct szedata2_cgmii_ibuf *);
+	volatile struct szedata2_cgmii_obuf *obuf = SZEDATA2_PCI_RESOURCE_PTR(
+			dev, SZEDATA2_CGMII_OBUF_BASE_OFF,
+			volatile struct szedata2_cgmii_obuf *);
+
+	cgmii_ibuf_disable(ibuf);
+	cgmii_obuf_disable(obuf);
 	return 0;
 }
 
@@ -1221,6 +1284,8 @@  eth_mac_addr_set(struct rte_eth_dev *dev __rte_unused,
 static struct eth_dev_ops ops = {
 		.dev_start          = eth_dev_start,
 		.dev_stop           = eth_dev_stop,
+		.dev_set_link_up    = eth_dev_set_link_up,
+		.dev_set_link_down  = eth_dev_set_link_down,
 		.dev_close          = eth_dev_close,
 		.dev_configure      = eth_dev_configure,
 		.dev_infos_get      = eth_dev_info,
@@ -1313,11 +1378,16 @@  rte_szedata2_eth_dev_init(struct rte_eth_dev *dev)
 	struct szedata *szedata_temp;
 	int ret;
 	uint32_t szedata2_index;
-	struct rte_pci_addr pciaddr = dev->pci_dev->addr;
+	struct rte_pci_addr *pci_addr = &dev->pci_dev->addr;
+	struct rte_pci_resource *pci_rsc =
+		&dev->pci_dev->mem_resource[PCI_RESOURCE_NUMBER];
+	char rsc_filename[PATH_MAX];
+	void *pci_resource_ptr = NULL;
+	int fd;
 
 	RTE_LOG(INFO, PMD, "Initializing szedata2 device (" PCI_PRI_FMT ")\n",
-			pciaddr.domain, pciaddr.bus, pciaddr.devid,
-			pciaddr.function);
+			pci_addr->domain, pci_addr->bus, pci_addr->devid,
+			pci_addr->function);
 
 	/* Get index of szedata2 device file and create path to device file */
 	ret = get_szedata2_index(dev, &szedata2_index);
@@ -1347,7 +1417,7 @@  rte_szedata2_eth_dev_init(struct rte_eth_dev *dev)
 			SZE2_DIR_TX);
 	szedata_close(szedata_temp);
 
-	RTE_LOG(INFO, PMD, "Available DMA channels RX: %u, TX: %u\n",
+	RTE_LOG(INFO, PMD, "Available DMA channels RX: %u TX: %u\n",
 			internals->max_rx_queues, internals->max_tx_queues);
 
 	/* Set rx, tx burst functions */
@@ -1366,25 +1436,77 @@  rte_szedata2_eth_dev_init(struct rte_eth_dev *dev)
 
 	rte_eth_copy_pci_info(dev, dev->pci_dev);
 
-	data->dev_link = pmd_link;
+	/* mmap pci resource0 file to rte_pci_resource structure */
+	if (dev->pci_dev->mem_resource[PCI_RESOURCE_NUMBER].phys_addr ==
+			0) {
+		RTE_LOG(ERR, PMD, "Missing resource%u file\n",
+				PCI_RESOURCE_NUMBER);
+		return -EINVAL;
+	}
+	snprintf(rsc_filename, PATH_MAX,
+		SYSFS_PCI_DEVICES "/" PCI_PRI_FMT "/resource%u",
+		pci_addr->domain, pci_addr->bus,
+		pci_addr->devid, pci_addr->function, PCI_RESOURCE_NUMBER);
+	fd = open(rsc_filename, O_RDWR);
+	if (fd < 0) {
+		RTE_LOG(ERR, PMD, "Could not open file %s\n", rsc_filename);
+		return -EINVAL;
+	}
+
+	pci_resource_ptr = mmap(0,
+			dev->pci_dev->mem_resource[PCI_RESOURCE_NUMBER].len,
+			PROT_READ | PROT_WRITE, MAP_SHARED, fd, 0);
+	close(fd);
+	if (pci_resource_ptr == NULL) {
+		RTE_LOG(ERR, PMD, "Could not mmap file %s (fd = %d)\n",
+				rsc_filename, fd);
+		return -EINVAL;
+	}
+	dev->pci_dev->mem_resource[PCI_RESOURCE_NUMBER].addr =
+		pci_resource_ptr;
+
+	RTE_LOG(DEBUG, PMD, "resource%u phys_addr = 0x%llx len = %llu "
+			"virt addr = %llx\n", PCI_RESOURCE_NUMBER,
+			(unsigned long long)pci_rsc->phys_addr,
+			(unsigned long long)pci_rsc->len,
+			(unsigned long long)pci_rsc->addr);
+
+	eth_link_update(dev, 0);
 
 	data->mac_addrs = rte_zmalloc(data->name, sizeof(struct ether_addr),
 			RTE_CACHE_LINE_SIZE);
 	if (data->mac_addrs == NULL) {
 		RTE_LOG(ERR, PMD, "Could not alloc space for MAC address!\n");
+		munmap(dev->pci_dev->mem_resource[PCI_RESOURCE_NUMBER].addr,
+			dev->pci_dev->mem_resource[PCI_RESOURCE_NUMBER].len);
 		return -EINVAL;
 	}
 
 	ether_addr_copy(&eth_addr, data->mac_addrs);
 
+	RTE_LOG(INFO, PMD, "szedata2 device ("
+			PCI_PRI_FMT ") successfully initialized\n",
+			pci_addr->domain, pci_addr->bus, pci_addr->devid,
+			pci_addr->function);
+
 	return 0;
 }
 
 static int
 rte_szedata2_eth_dev_uninit(struct rte_eth_dev *dev)
 {
+	struct rte_pci_addr *pci_addr = &dev->pci_dev->addr;
+
 	rte_free(dev->data->mac_addrs);
 	dev->data->mac_addrs = NULL;
+	munmap(dev->pci_dev->mem_resource[PCI_RESOURCE_NUMBER].addr,
+		dev->pci_dev->mem_resource[PCI_RESOURCE_NUMBER].len);
+
+	RTE_LOG(INFO, PMD, "szedata2 device ("
+			PCI_PRI_FMT ") successfully uninitialized\n",
+			pci_addr->domain, pci_addr->bus, pci_addr->devid,
+			pci_addr->function);
+
 	return 0;
 }
 
diff --git a/drivers/net/szedata2/rte_eth_szedata2.h b/drivers/net/szedata2/rte_eth_szedata2.h
index 7137ba2..39d1c48 100644
--- a/drivers/net/szedata2/rte_eth_szedata2.h
+++ b/drivers/net/szedata2/rte_eth_szedata2.h
@@ -1,7 +1,7 @@ 
 /*-
  *   BSD LICENSE
  *
- *   Copyright (c) 2015 CESNET
+ *   Copyright (c) 2015 - 2016 CESNET
  *   All rights reserved.
  *
  *   Redistribution and use in source and binary forms, with or without
@@ -34,6 +34,10 @@ 
 #ifndef RTE_PMD_SZEDATA2_H_
 #define RTE_PMD_SZEDATA2_H_
 
+#include <stdbool.h>
+
+#include <rte_byteorder.h>
+
 /* PCI Vendor ID */
 #define PCI_VENDOR_ID_NETCOPE 0x1b26
 
@@ -42,6 +46,9 @@ 
 #define PCI_DEVICE_ID_NETCOPE_COMBO100G 0xc1c1
 #define PCI_DEVICE_ID_NETCOPE_COMBO100G2 0xc2c1
 
+/* number of PCI resource used by COMBO card */
+#define PCI_RESOURCE_NUMBER 0
+
 /* szedata2_packet header length == 4 bytes == 2B segment size + 2B hw size */
 #define RTE_SZE2_PACKET_HEADER_SIZE 4
 
@@ -106,5 +113,311 @@  struct szedata {
 	int                         numa_node;
 };
 
+/*
+ * @return Byte from PCI resource at offset "offset".
+ */
+static inline uint8_t
+pci_resource_read8(struct rte_eth_dev *dev, uint32_t offset)
+{
+	return *((uint8_t *)((uint8_t *)
+			dev->pci_dev->mem_resource[PCI_RESOURCE_NUMBER].addr +
+			offset));
+}
+
+/*
+ * @return Two bytes from PCI resource starting at offset "offset".
+ */
+static inline uint16_t
+pci_resource_read16(struct rte_eth_dev *dev, uint32_t offset)
+{
+	return rte_le_to_cpu_16(*((uint16_t *)((uint8_t *)
+			dev->pci_dev->mem_resource[PCI_RESOURCE_NUMBER].addr +
+			offset)));
+}
+
+/*
+ * @return Four bytes from PCI resource starting at offset "offset".
+ */
+static inline uint32_t
+pci_resource_read32(struct rte_eth_dev *dev, uint32_t offset)
+{
+	return rte_le_to_cpu_32(*((uint32_t *)((uint8_t *)
+			dev->pci_dev->mem_resource[PCI_RESOURCE_NUMBER].addr +
+			offset)));
+}
+
+/*
+ * @return Eight bytes from PCI resource starting at offset "offset".
+ */
+static inline uint64_t
+pci_resource_read64(struct rte_eth_dev *dev, uint32_t offset)
+{
+	return rte_le_to_cpu_64(*((uint64_t *)((uint8_t *)
+			dev->pci_dev->mem_resource[PCI_RESOURCE_NUMBER].addr +
+			offset)));
+}
+
+/*
+ * Write one byte to PCI resource address space at offset "offset".
+ */
+static inline void
+pci_resource_write8(struct rte_eth_dev *dev, uint32_t offset, uint8_t val)
+{
+	*((uint8_t *)((uint8_t *)
+			dev->pci_dev->mem_resource[PCI_RESOURCE_NUMBER].addr +
+			offset)) = val;
+}
+
+/*
+ * Write two bytes to PCI resource address space at offset "offset".
+ */
+static inline void
+pci_resource_write16(struct rte_eth_dev *dev, uint32_t offset, uint16_t val)
+{
+	*((uint16_t *)((uint8_t *)
+			dev->pci_dev->mem_resource[PCI_RESOURCE_NUMBER].addr +
+			offset)) = rte_cpu_to_le_16(val);
+}
+
+/*
+ * Write four bytes to PCI resource address space at offset "offset".
+ */
+static inline void
+pci_resource_write32(struct rte_eth_dev *dev, uint32_t offset, uint32_t val)
+{
+	*((uint32_t *)((uint8_t *)
+			dev->pci_dev->mem_resource[PCI_RESOURCE_NUMBER].addr +
+			offset)) = rte_cpu_to_le_32(val);
+}
+
+/*
+ * Write eight bytes to PCI resource address space at offset "offset".
+ */
+static inline void
+pci_resource_write64(struct rte_eth_dev *dev, uint32_t offset, uint64_t val)
+{
+	*((uint64_t *)((uint8_t *)
+			dev->pci_dev->mem_resource[PCI_RESOURCE_NUMBER].addr +
+			offset)) = rte_cpu_to_le_64(val);
+}
+
+#define SZEDATA2_PCI_RESOURCE_PTR(dev, offset, type) \
+	((type)((uint8_t *) \
+	((dev)->pci_dev->mem_resource[PCI_RESOURCE_NUMBER].addr) \
+	+ (offset)))
+
+enum szedata2_link_speed {
+	SZEDATA2_LINK_SPEED_DEFAULT = 0,
+	SZEDATA2_LINK_SPEED_10G,
+	SZEDATA2_LINK_SPEED_40G,
+	SZEDATA2_LINK_SPEED_100G,
+};
+
+/*
+ * Structure describes CGMII IBUF address space
+ */
+struct szedata2_cgmii_ibuf {
+	/** Total Received Frames Counter low part */
+	uint32_t trfcl;
+	/** Correct Frames Counter low part */
+	uint32_t cfcl;
+	/** Discarded Frames Counter low part */
+	uint32_t dfcl;
+	/** Counter of frames discarded due to buffer overflow low part */
+	uint32_t bodfcl;
+	/** Total Received Frames Counter high part */
+	uint32_t trfch;
+	/** Correct Frames Counter high part */
+	uint32_t cfch;
+	/** Discarded Frames Counter high part */
+	uint32_t dfch;
+	/** Counter of frames discarded due to buffer overflow high part */
+	uint32_t bodfch;
+	/** IBUF enable register */
+	uint32_t ibuf_en;
+	/** Error mask register */
+	uint32_t err_mask;
+	/** IBUF status register */
+	uint32_t ibuf_st;
+	/** IBUF command register */
+	uint32_t ibuf_cmd;
+	/** Minimum frame length allowed */
+	uint32_t mfla;
+	/** Frame MTU */
+	uint32_t mtu;
+	/** MAC address check mode */
+	uint32_t mac_chmode;
+	/** Octets Received OK Counter low part */
+	uint32_t orocl;
+	/** Octets Received OK Counter high part */
+	uint32_t oroch;
+} __rte_packed;
+
+/* Offset of CGMII IBUF memory for MAC addresses */
+#define SZEDATA2_CGMII_IBUF_MAC_MEM_OFF 0x80
+
+/*
+ * @return
+ *     true if IBUF is enabled
+ *     false if IBUF is disabled
+ */
+static inline bool
+cgmii_ibuf_is_enabled(volatile struct szedata2_cgmii_ibuf *ibuf)
+{
+	return ((rte_le_to_cpu_32(ibuf->ibuf_en) & 0x1) != 0) ? true : false;
+}
+
+/*
+ * Enables IBUF.
+ */
+static inline void
+cgmii_ibuf_enable(volatile struct szedata2_cgmii_ibuf *ibuf)
+{
+	ibuf->ibuf_en =
+		rte_cpu_to_le_32(rte_le_to_cpu_32(ibuf->ibuf_en) | 0x1);
+}
+
+/*
+ * Disables IBUF.
+ */
+static inline void
+cgmii_ibuf_disable(volatile struct szedata2_cgmii_ibuf *ibuf)
+{
+	ibuf->ibuf_en =
+		rte_cpu_to_le_32(rte_le_to_cpu_32(ibuf->ibuf_en) & ~0x1);
+}
+
+/*
+ * @return
+ *     true if ibuf link is up
+ *     false if ibuf link is down
+ */
+static inline bool
+cgmii_ibuf_is_link_up(volatile struct szedata2_cgmii_ibuf *ibuf)
+{
+	return ((rte_le_to_cpu_32(ibuf->ibuf_st) & 0x80) != 0) ? true : false;
+}
+
+/*
+ * Structure describes CGMII OBUF address space
+ */
+struct szedata2_cgmii_obuf {
+	/** Total Sent Frames Counter low part */
+	uint32_t tsfcl;
+	/** Octets Sent Counter low part */
+	uint32_t oscl;
+	/** Total Discarded Frames Counter low part */
+	uint32_t tdfcl;
+	/** reserved */
+	uint32_t reserved1;
+	/** Total Sent Frames Counter high part */
+	uint32_t tsfch;
+	/** Octets Sent Counter high part */
+	uint32_t osch;
+	/** Total Discarded Frames Counter high part */
+	uint32_t tdfch;
+	/** reserved */
+	uint32_t reserved2;
+	/** OBUF enable register */
+	uint32_t obuf_en;
+	/** reserved */
+	uint64_t reserved3;
+	/** OBUF control register */
+	uint32_t ctrl;
+	/** OBUF status register */
+	uint32_t obuf_st;
+} __rte_packed;
+
+/*
+ * @return
+ *     true if OBUF is enabled
+ *     false if OBUF is disabled
+ */
+static inline bool
+cgmii_obuf_is_enabled(volatile struct szedata2_cgmii_obuf *obuf)
+{
+	return ((rte_le_to_cpu_32(obuf->obuf_en) & 0x1) != 0) ? true : false;
+}
+
+/*
+ * Enables OBUF.
+ */
+static inline void
+cgmii_obuf_enable(volatile struct szedata2_cgmii_obuf *obuf)
+{
+	obuf->obuf_en =
+		rte_cpu_to_le_32(rte_le_to_cpu_32(obuf->obuf_en) | 0x1);
+}
+
+/*
+ * Disables OBUF.
+ */
+static inline void
+cgmii_obuf_disable(volatile struct szedata2_cgmii_obuf *obuf)
+{
+	obuf->obuf_en =
+		rte_cpu_to_le_32(rte_le_to_cpu_32(obuf->obuf_en) & ~0x1);
+}
+
+/*
+ * Function takes value from IBUF status register. Values in IBUF and OBUF
+ * should be same.
+ *
+ * @return Link speed constant.
+ */
+static inline enum szedata2_link_speed
+cgmii_link_speed(volatile struct szedata2_cgmii_ibuf *ibuf)
+{
+	uint32_t speed = (rte_le_to_cpu_32(ibuf->ibuf_st) & 0x70) >> 4;
+	switch (speed) {
+	case 0x03:
+		return SZEDATA2_LINK_SPEED_10G;
+	case 0x04:
+		return SZEDATA2_LINK_SPEED_40G;
+	case 0x05:
+		return SZEDATA2_LINK_SPEED_100G;
+	default:
+		return SZEDATA2_LINK_SPEED_DEFAULT;
+	}
+}
+
+/*
+ * IBUFs and OBUFs can generally be located at different offsets in different
+ * firmwares.
+ * This part defines base offsets of IBUFs and OBUFs through various firmwares.
+ * Currently one firmware type is supported.
+ * Type of firmware is set through configuration option
+ * CONFIG_RTE_LIBRTE_PMD_SZEDATA_AS.
+ * Possible values are:
+ * 0 - for firmwares:
+ *     NIC_100G1_LR4
+ *     HANIC_100G1_LR4
+ *     HANIC_100G1_SR10
+ */
+#if !defined(RTE_LIBRTE_PMD_SZEDATA2_AS)
+#error "RTE_LIBRTE_PMD_SZEDATA2_AS has to be defined"
+#elif RTE_LIBRTE_PMD_SZEDATA2_AS == 0
+
+/*
+ * CGMII IBUF offset from the beginning of PCI resource address space.
+ */
+#define SZEDATA2_CGMII_IBUF_BASE_OFF 0x8000
+/*
+ * Size of CGMII IBUF.
+ */
+#define SZEDATA2_CGMII_IBUF_SIZE 0x200
+
+/*
+ * GCMII OBUF offset from the beginning of PCI resource address space.
+ */
+#define SZEDATA2_CGMII_OBUF_BASE_OFF 0x9000
+/*
+ * Size of CGMII OBUF.
+ */
+#define SZEDATA2_CGMII_OBUF_SIZE 0x100
+
+#else
+#error "RTE_LIBRTE_PMD_SZEDATA2_AS has wrong value, see comments in config file"
+#endif
 
 #endif