From patchwork Thu Jan 14 06:13:19 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhihong Wang X-Patchwork-Id: 9851 Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [IPv6:::1]) by dpdk.org (Postfix) with ESMTP id D111A8E90; Thu, 14 Jan 2016 14:16:47 +0100 (CET) Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by dpdk.org (Postfix) with ESMTP id E71C5F72 for ; Thu, 14 Jan 2016 14:16:45 +0100 (CET) Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga104.fm.intel.com with ESMTP; 14 Jan 2016 05:16:45 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.22,294,1449561600"; d="scan'208";a="881268041" Received: from unknown (HELO dpdk5.sh.intel.com) ([10.239.129.244]) by fmsmga001.fm.intel.com with ESMTP; 14 Jan 2016 05:16:44 -0800 From: Zhihong Wang To: dev@dpdk.org Date: Thu, 14 Jan 2016 01:13:19 -0500 Message-Id: <1452752002-107586-2-git-send-email-zhihong.wang@intel.com> X-Mailer: git-send-email 2.5.0 In-Reply-To: <1452752002-107586-1-git-send-email-zhihong.wang@intel.com> References: <1452752002-107586-1-git-send-email-zhihong.wang@intel.com> Subject: [dpdk-dev] [PATCH 1/4] lib/librte_eal: Identify AVX512 CPU flag X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Read CPUID to check if AVX512 is supported by CPU. Signed-off-by: Zhihong Wang --- lib/librte_eal/common/include/arch/x86/rte_cpuflags.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/lib/librte_eal/common/include/arch/x86/rte_cpuflags.h b/lib/librte_eal/common/include/arch/x86/rte_cpuflags.h index dd56553..89c0d9d 100644 --- a/lib/librte_eal/common/include/arch/x86/rte_cpuflags.h +++ b/lib/librte_eal/common/include/arch/x86/rte_cpuflags.h @@ -131,6 +131,7 @@ enum rte_cpu_flag_t { RTE_CPUFLAG_ERMS, /**< ERMS */ RTE_CPUFLAG_INVPCID, /**< INVPCID */ RTE_CPUFLAG_RTM, /**< Transactional memory */ + RTE_CPUFLAG_AVX512F, /**< AVX512F */ /* (EAX 80000001h) ECX features */ RTE_CPUFLAG_LAHF_SAHF, /**< LAHF_SAHF */ @@ -238,6 +239,7 @@ static const struct feature_entry cpu_feature_table[] = { FEAT_DEF(ERMS, 0x00000007, 0, RTE_REG_EBX, 8) FEAT_DEF(INVPCID, 0x00000007, 0, RTE_REG_EBX, 10) FEAT_DEF(RTM, 0x00000007, 0, RTE_REG_EBX, 11) + FEAT_DEF(AVX512F, 0x00000007, 0, RTE_REG_EBX, 16) FEAT_DEF(LAHF_SAHF, 0x80000001, 0, RTE_REG_ECX, 0) FEAT_DEF(LZCNT, 0x80000001, 0, RTE_REG_ECX, 4)