diff mbox

[dpdk-dev,1/3] i40e: enable extended tag

Message ID 1450665486-8335-2-git-send-email-helin.zhang@intel.com (mailing list archive)
State Superseded, archived
Delegated to: Thomas Monjalon
Headers show

Commit Message

Helin Zhang Dec. 21, 2015, 2:38 a.m. UTC
PCIe feature of 'Extended Tag' is important for 40G performance.
It adds its enabling during each port initialization, to ensure
the high performance.

Signed-off-by: Helin Zhang <helin.zhang@intel.com>
---
 doc/guides/rel_notes/release_2_3.rst |  5 +++
 drivers/net/i40e/i40e_ethdev.c       | 67 ++++++++++++++++++++++++++++++++++--
 2 files changed, 69 insertions(+), 3 deletions(-)

Comments

Jingjing Wu Jan. 22, 2016, 1:34 a.m. UTC | #1
Hi

>   */
>  static void
> -i40e_hw_init(struct i40e_hw *hw)
> +i40e_hw_init(struct rte_eth_dev *dev)
>  {
> +	struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data-
> >dev_private);
> +
> +	i40e_enable_extended_tag(dev);
If the function i40e_enable_extended_tag is only used here without
Checking the return value, why not define it as void?

Thanks
Jingjing
> +
>  	/* clear the PF Queue Filter control register */
>  	I40E_WRITE_REG(hw, I40E_PFQF_CTL_0, 0);
> 
> --
> 1.9.3
Thomas Monjalon Jan. 22, 2016, 10:26 a.m. UTC | #2
2015-12-21 10:38, Helin Zhang:
> PCIe feature of 'Extended Tag' is important for 40G performance.
> It adds its enabling during each port initialization, to ensure
> the high performance.

If it's so important, why the values are not documented?
Please start to fill a file doc/guides/nics/i40e.rst to explain
how the device works.
Thanks
Helin Zhang Jan. 24, 2016, 3:25 a.m. UTC | #3
Hi Thomas

It has already been mentioned in getting started guide for a long time.
Are you suggesting to move into i40e specifically? Thanks!

Regards,
Helin

-----Original Message-----
From: Thomas Monjalon [mailto:thomas.monjalon@6wind.com] 
Sent: Friday, January 22, 2016 6:27 PM
To: Zhang, Helin <helin.zhang@intel.com>
Cc: dev@dpdk.org
Subject: Re: [dpdk-dev] [PATCH 1/3] i40e: enable extended tag

2015-12-21 10:38, Helin Zhang:
> PCIe feature of 'Extended Tag' is important for 40G performance.
> It adds its enabling during each port initialization, to ensure the 
> high performance.

If it's so important, why the values are not documented?
Please start to fill a file doc/guides/nics/i40e.rst to explain how the device works.
Thanks
Thomas Monjalon Jan. 25, 2016, 9:16 a.m. UTC | #4
> From: Thomas Monjalon [mailto:thomas.monjalon@6wind.com] 
> > 2015-12-21 10:38, Helin Zhang:
> > > PCIe feature of 'Extended Tag' is important for 40G performance.
> > > It adds its enabling during each port initialization, to ensure the
> > > high performance.
> > 
> > If it's so important, why the values are not documented?
> > Please start to fill a file doc/guides/nics/i40e.rst to explain how the
> > device works. Thanks
> 
> It has already been mentioned in getting started guide for a long time.
> Are you suggesting to move into i40e specifically? Thanks!

Yes you're right. I had forgotten that:
http://dpdk.org/doc/guides-2.2/linux_gsg/enable_func.html#enabling-extended-tag-and-setting-max-read-request-size

Yes, it would be better moved into an i40e doc.
And maybe max_read_request_size may be commented to give advices on values.
Thanks
Helin Zhang Jan. 26, 2016, 12:29 a.m. UTC | #5
> -----Original Message-----
> From: Thomas Monjalon [mailto:thomas.monjalon@6wind.com]
> Sent: Monday, January 25, 2016 5:17 PM
> To: Zhang, Helin
> Cc: dev@dpdk.org
> Subject: Re: [dpdk-dev] [PATCH 1/3] i40e: enable extended tag
> 
> > From: Thomas Monjalon [mailto:thomas.monjalon@6wind.com]
> > > 2015-12-21 10:38, Helin Zhang:
> > > > PCIe feature of 'Extended Tag' is important for 40G performance.
> > > > It adds its enabling during each port initialization, to ensure
> > > > the high performance.
> > >
> > > If it's so important, why the values are not documented?
> > > Please start to fill a file doc/guides/nics/i40e.rst to explain how
> > > the device works. Thanks
> >
> > It has already been mentioned in getting started guide for a long time.
> > Are you suggesting to move into i40e specifically? Thanks!
> 
> Yes you're right. I had forgotten that:
> http://dpdk.org/doc/guides-2.2/linux_gsg/enable_func.html#enabling-
> extended-tag-and-setting-max-read-request-size
> 
> Yes, it would be better moved into an i40e doc.
> And maybe max_read_request_size may be commented to give advices on
> values.
> Thanks

OK. Good idea, and I will move that soon later. Thanks!

Regards,
Helin
diff mbox

Patch

diff --git a/doc/guides/rel_notes/release_2_3.rst b/doc/guides/rel_notes/release_2_3.rst
index 99de186..efd258b 100644
--- a/doc/guides/rel_notes/release_2_3.rst
+++ b/doc/guides/rel_notes/release_2_3.rst
@@ -4,6 +4,11 @@  DPDK Release 2.3
 New Features
 ------------
 
+* **i40e: Enabled extended tag.**
+
+  It enabled extended tag by checking and writing corresponding PCI config
+  space bytes, to boost the performance.
+
 
 Resolved Issues
 ---------------
diff --git a/drivers/net/i40e/i40e_ethdev.c b/drivers/net/i40e/i40e_ethdev.c
index bf6220d..973aca8 100644
--- a/drivers/net/i40e/i40e_ethdev.c
+++ b/drivers/net/i40e/i40e_ethdev.c
@@ -273,6 +273,17 @@ 
 #define I40E_INSET_IPV6_TC_MASK       0x0009F00FUL
 #define I40E_INSET_IPV6_NEXT_HDR_MASK 0x000C00FFUL
 
+/* PCI offset for querying capability */
+#define PCI_DEV_CAP_REG            0xA4
+/* PCI offset for enabling/disabling Extended Tag */
+#define PCI_DEV_CTRL_REG           0xA8
+/* Bit mask of Extended Tag capability */
+#define PCI_DEV_CAP_EXT_TAG_MASK   0x20
+/* Bit shift of Extended Tag enable/disable */
+#define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
+/* Bit mask of Extended Tag enable/disable */
+#define PCI_DEV_CTRL_EXT_TAG_MASK  (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
+
 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
 static int i40e_dev_configure(struct rte_eth_dev *dev);
@@ -386,7 +397,7 @@  static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
 				  struct rte_eth_dcb_info *dcb_info);
 static void i40e_configure_registers(struct i40e_hw *hw);
-static void i40e_hw_init(struct i40e_hw *hw);
+static void i40e_hw_init(struct rte_eth_dev *dev);
 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
 			struct rte_eth_mirror_conf *mirror_conf,
@@ -765,7 +776,7 @@  eth_i40e_dev_init(struct rte_eth_dev *dev)
 	i40e_clear_hw(hw);
 
 	/* Initialize the hardware */
-	i40e_hw_init(hw);
+	i40e_hw_init(dev);
 
 	/* Reset here to make sure all is clean for each PF */
 	ret = i40e_pf_reset(hw);
@@ -7262,13 +7273,63 @@  i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 }
 
 /*
+ * Check and enable Extended Tag.
+ * Enabling Extended Tag is important for 40G performance.
+ */
+static int
+i40e_enable_extended_tag(struct rte_eth_dev *dev)
+{
+	uint32_t buf = 0;
+	int ret;
+
+	ret = rte_eal_pci_read_config(dev->pci_dev, &buf, sizeof(buf),
+				      PCI_DEV_CAP_REG);
+	if (ret < 0) {
+		PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
+			    PCI_DEV_CAP_REG);
+		return -1;
+	}
+	if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
+		PMD_DRV_LOG(ERR, "Does not support Extended Tag");
+		return -1;
+	}
+
+	buf = 0;
+	ret = rte_eal_pci_read_config(dev->pci_dev, &buf, sizeof(buf),
+				      PCI_DEV_CTRL_REG);
+	if (ret < 0) {
+		PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
+			    PCI_DEV_CTRL_REG);
+		return -1;
+	}
+	if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
+		PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
+		return 0;
+	}
+	buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
+	ret = rte_eal_pci_write_config(dev->pci_dev, &buf, sizeof(buf),
+				       PCI_DEV_CTRL_REG);
+	if (ret < 0) {
+		PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
+			    PCI_DEV_CTRL_REG);
+		return -1;
+	}
+
+	return 0;
+}
+
+/*
  * As some registers wouldn't be reset unless a global hardware reset,
  * hardware initialization is needed to put those registers into an
  * expected initial state.
  */
 static void
-i40e_hw_init(struct i40e_hw *hw)
+i40e_hw_init(struct rte_eth_dev *dev)
 {
+	struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
+
+	i40e_enable_extended_tag(dev);
+
 	/* clear the PF Queue Filter control register */
 	I40E_WRITE_REG(hw, I40E_PFQF_CTL_0, 0);