| Message ID | 1446565921-18088-1-git-send-email-jerin.jacob@caviumnetworks.com (mailing list archive) |
|---|---|
| State | Rejected, archived |
| Headers |
Return-Path: <dev-bounces@dpdk.org> X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [IPv6:::1]) by dpdk.org (Postfix) with ESMTP id BF52458F1; Tue, 3 Nov 2015 16:52:32 +0100 (CET) Received: from na01-bn1-obe.outbound.protection.outlook.com (mail-bn1bon0094.outbound.protection.outlook.com [157.56.111.94]) by dpdk.org (Postfix) with ESMTP id C7AE537AF for <dev@dpdk.org>; Tue, 3 Nov 2015 16:52:30 +0100 (CET) Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=Jerin.Jacob@caviumnetworks.com; Received: from localhost.caveonetworks.com (111.93.218.67) by SN1PR0701MB1982.namprd07.prod.outlook.com (10.163.131.21) with Microsoft SMTP Server (TLS) id 15.1.312.18; Tue, 3 Nov 2015 15:52:27 +0000 From: Jerin Jacob <jerin.jacob@caviumnetworks.com> To: <dev@dpdk.org> Date: Tue, 3 Nov 2015 21:22:01 +0530 Message-ID: <1446565921-18088-1-git-send-email-jerin.jacob@caviumnetworks.com> X-Mailer: git-send-email 2.1.0 MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [111.93.218.67] X-ClientProxiedBy: BLUPR0601CA0006.namprd06.prod.outlook.com (25.163.210.16) To SN1PR0701MB1982.namprd07.prod.outlook.com (25.163.131.21) X-Microsoft-Exchange-Diagnostics: 1; SN1PR0701MB1982; 2:14GnzRBKo4LAcUSUW3qFBx96ESXknizi4Q+vopFi3fgtiqOxBVetZoJ+Cd4Fwcgp2VSYXm1/RKK3RIA/ffbD0dCtMJ070EhYSjl4Wv6pjjCb/6AMdEadwJSj9Xo6IiLXAyb/LOMEyKvpeFMFol3AccZxyC0pg3uoE94zjLlvFtI=; 3:qtIoOjcECkh7hfnqmyzgLm4EQ2jwF+QlfQD2MqIxEGAszNj5Nmu49GLFdOpgbszfrk/IzJYFMzdWKHsoIM3eGYQBAFrKb3RrGZJLD95wA56HgVC5d6jjITywQGDLbAzPb2EwrY+7S7S6AYBDHowPEA==; 25:9ySAPl11zbAc613DeVVeStx67pY5ToedQt8nTPCC7AWukO0lZY3MuxSn8rJF+6dGYQu3/mxbglnLWxb04QXtwC+FooqUH7IrAbwfXV+Be3nbuE3CfN/NKEAHCLUIzFqXMU4y8isNIsS7DR+ECipJ2+EBHwF+uO+J7QneqQ5/7NbKSniBMLTqxzQHyt6HEF8arsTI3TyfqfIAgn7K4wNKavxgPt2d+OBqqqsskcILCXkfptytTYF3Xa8Osxt8b2CYBJs0CZHfF6s3Xo/e9+m9JQ== X-Microsoft-Antispam: UriScan:;BCL:0;PCL:0;RULEID:;SRVR:SN1PR0701MB1982; X-Microsoft-Exchange-Diagnostics: 1; SN1PR0701MB1982; 20:q5nSbcJXKTfrcYenkx2Wt7kBSGgvdlXiTmi4FO/gqGsATPVviHfaGrtYoFatoDmlHl3iXAQv09e35e9zQDhMUM1UIa/7cLvOEHqhgjoA6eOvWORbt6B3PY+FBPCumbnPtSD+DIvE2s52Tm4SA5LR+bCYyr1mTOX+DgxzuL7vJRFhny57xhjqhZJ6ZeHOyPyikmZ4FUC8hKgdoPqOPSMaABIuK4r6QqhVVQIDrkbX30nEah5CsCdvklrFDTsP6D1y/4hb6Kq5ShEZaZY3+Tt5rpp73aR4fo8uLaQakY39/P83didu0bP32mDvsUVjrFy3QtTjBfl5Zcxtsslj4dL2FyvDrQMgZwwtkwiHqeMcFPlZ+eGDQfkkJ5Q8RcOako6kq9dRm7NSLGR/kmZoc1bGcBHnaZIvRNz6Y0i/HV59f9HHrBbXgS7Td8RT5bc02SmPkrd2RlwSnNW1MNTQPOBYmyteMaGgti9vOxAPQFicXFHi9U2ux0i9ZZMBaPtIyxGibq9Va9GlzxjKHhj3tKHMJeV/6u+WkVL9+ui6wnfCpTMRPtnCrhPVQcLas1Z8JskUU1/bipIF68A1tGBhDO2+vIHPw5EaumAhqg+uNE95Tpk= X-Microsoft-Antispam-PRVS: <SN1PR0701MB198287B715C0B82F90F663A98C2B0@SN1PR0701MB1982.namprd07.prod.outlook.com> X-Exchange-Antispam-Report-Test: UriScan:(236414709691187); X-Exchange-Antispam-Report-CFA-Test: BCL:0; PCL:0; RULEID:(601004)(2401047)(5005006)(8121501046)(520078)(10201501046)(3002001); SRVR:SN1PR0701MB1982; BCL:0; PCL:0; RULEID:; SRVR:SN1PR0701MB1982; X-Microsoft-Exchange-Diagnostics: 1; SN1PR0701MB1982; 4:P9hN53bOZcQIxcTJoi/E2OvTLOqsoyhKF1pyTbq831X+zLM8Y9MwsX964TsqP0VMnP99IfnB1QXW3/2sPJzLnS9NXmHIvfe9zWM7BFQaSdlSaPFf4h6VqS78VLLZvdGma6zTLknA+/fmMVsCHycy5CFF0rQTmcyMeymPqiKoz821ToYPqlWkAQ1kQcM3DgqA7MkVgIPm21eT8H4puiZbqoybLeKfusyON+kUU1oL5HbZjgJPxd/3pXQH2GzBqCqa3k3pW3AL/T3EaHcVXyrO/rbsp5To7AvH3501W+mK0sDjqyMUriDDwCHZ3TEaAmqa6d5Wu7k0jZ9sqX1lAO9hsxkI2GLsaXGR/X5juJl6KksVxKptSS3uIhjQVazGH0/3 X-Forefront-PRVS: 0749DC2CE6 X-Forefront-Antispam-Report: SFV:NSPM; SFS:(10009020)(979002)(6009001)(6069001)(189002)(199003)(76506005)(66066001)(5001960100002)(33646002)(50226001)(50986999)(5009440100003)(81156007)(69596002)(40100003)(97736004)(36756003)(47776003)(110136002)(229853001)(101416001)(4001430100002)(19580405001)(92566002)(5008740100001)(77096005)(86362001)(87976001)(122386002)(107886002)(106356001)(105586002)(5003940100001)(5007970100001)(48376002)(50466002)(19580395003)(53416004)(42186005)(2351001)(189998001)(5004730100002)(7099028)(969003)(989001)(999001)(1009001)(1019001); DIR:OUT; SFP:1101; SCL:1; SRVR:SN1PR0701MB1982; H:localhost.caveonetworks.com; FPR:; SPF:None; PTR:InfoNoRecords; MX:1; A:1; LANG:en; Received-SPF: None (protection.outlook.com: caviumnetworks.com does not designate permitted sender hosts) X-Microsoft-Exchange-Diagnostics: =?us-ascii?Q?1; SN1PR0701MB1982; 23:5EGXvdeskEanm4b1VVGmTUQyWWx0yi0CBLamWzP?= =?us-ascii?Q?6fze9E4kn2DUVlx2df7kfb2XvVRnqj+0T+f8P1X7aGsHO/4vVcwLbhaz2MEv?= =?us-ascii?Q?jQCu4amPnIKolRGgQD75IX3VTp2ABdCsTnKZB4sc05sGfkk4ljNQchMQ6qsF?= =?us-ascii?Q?7oXRnkFaFu28X+nW/WLSHp4XXkdu8DuMM5AuWZwUaysrm9nssCDreXhoff06?= =?us-ascii?Q?GvZ67XpQiwNkAkvdk6ar5d822d6RGHYofcOxaEh2EIDXhFQpihnCOaWAeTwb?= =?us-ascii?Q?LHNsp5ZUchEIS52yY1aX/8IOuqW8tlZHz+czNApTFT9q4wITF7iWmqClfbBx?= =?us-ascii?Q?ZmUZXOLy/fn1DMBZypCfwOEz0bCN+LjCAiMm89VDdSIkRy3pAS0a2A95r5w2?= =?us-ascii?Q?G7ZwMgMGae9U4qpQuUZATkgoSEngERXXQpyMvF6jdW4zZdJ7pZjeohFsAOPz?= =?us-ascii?Q?abq9S8OIjZwwtTZtou6dhfsjdhk4qSrV1CP/PKNfSMRSN41OjI8eSyk+fZxy?= =?us-ascii?Q?Y5yrxZqD5kVJ4eJ3UGPZ1x+X8uRQ4dp2y7D9rM80b4TCGx+zIUGdO19/tJJk?= =?us-ascii?Q?7J2bTL/gNWO1z7kJK7ZQ+7y9lC0ax3S97ZPYA1YrTlxfzoiNdh8YQVf/xKz8?= =?us-ascii?Q?fTkt2Eg5vpoEwCuTPx99/corxXxjYipuMomtP/6EQKuGvCRVpKTKi+SgKMep?= =?us-ascii?Q?hZrFq2NYnB9/12v40Qo0eZVKpkhxngUj7+x9opei97FH6XbrY6QVdrkafhuf?= =?us-ascii?Q?TPHzjWQS+F8rc1hJuXFDntdozV4UxGP+leIZNWG4ULQSb7pneAc5NhtbZqrx?= =?us-ascii?Q?LnUa2ipgq6pzOq1ibBQYt+5PD0WTwiZqcH8KC2JBx8KJez5pNCQGYht7X8Mb?= =?us-ascii?Q?eiUv15wr7O5N/R5ur8swFMQ5qxrLPwvPZr+AWlHTmRNbE1hCTmaviA3agbBE?= =?us-ascii?Q?63VE39Rjq46nKbz6qqqcZNKMdXW29utqz5IAVDZXI3ldeXJ7kBZBSb53t3Tm?= =?us-ascii?Q?eJst6T8k5vrrZDbhHg9O+RLekqRcSU5jqLvArFvkAZ7LztSYl6jzBmCJ+0z3?= =?us-ascii?Q?RBIPYzghGllX87JbSzxtLINMS3XQ14+hPhLACUHscC/Kc8tObh6pFpbILc+0?= =?us-ascii?Q?3uPjMNxoXUB0zwl0+kJAQKf3UwMywz6QvKgH42BdDi0qV2J6fDFhMXzB9zGO?= =?us-ascii?Q?fIbA6a4KFDKbdCabZYW1fxpyaHV/p+82mNSkTtl6dvJCchIcZG7btKa5QiSs?= =?us-ascii?Q?JUWbiMg5gCkFQyb8Ntdk=3D?= X-Microsoft-Exchange-Diagnostics: 1; SN1PR0701MB1982; 5:W1fhsZ/iEhUH4iG0lbPyr19U3mZfz99/NvVkUlTFdfnsp2eizpz9OQFwDNObGaAng1Qik/28iWSrM/+GVZ0l/1pVsLiCKmvCGtxwPl50ZejxrzrBwTqVJYi+GQyIDTKo4trfzuMmmz8/KqcjhdZy5w==; 24:9juIHZ9p8ZJelR2XI14d1DLRAqIBJmhJDvKRbGudHGkmQbKCLxgcAIB5DwNWKfLNehXDCz2AmDo7d/F5HRkBAmXIH0k0nNXe4xnN3wWGZes=; 20:hbak8dqkTEaoERLizgy/7idaxYzHHHh0Bm/SxQUlH7Hq82UfPYUiIUm+jR6BNahln+aGlkanrzJuugU/s7PILA== SpamDiagnosticOutput: 1:23 SpamDiagnosticMetadata: NSPM X-OriginatorOrg: caviumnetworks.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Nov 2015 15:52:27.2800 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN1PR0701MB1982 Subject: [dpdk-dev] [RFC ][PATCH] Introduce RTE_ARCH_STRONGLY_ORDERED_MEM_OPS configuration parameter X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK <dev.dpdk.org> List-Unsubscribe: <http://dpdk.org/ml/options/dev>, <mailto:dev-request@dpdk.org?subject=unsubscribe> List-Archive: <http://dpdk.org/ml/archives/dev/> List-Post: <mailto:dev@dpdk.org> List-Help: <mailto:dev-request@dpdk.org?subject=help> List-Subscribe: <http://dpdk.org/ml/listinfo/dev>, <mailto:dev-request@dpdk.org?subject=subscribe> Errors-To: dev-bounces@dpdk.org Sender: "dev" <dev-bounces@dpdk.org> |
Commit Message
Jerin Jacob
Nov. 3, 2015, 3:52 p.m. UTC
rte_ring implementation needs explicit memory barrier
in weakly ordered architecture like ARM unlike
strongly ordered architecture like X86
Introducing RTE_ARCH_STRONGLY_ORDERED_MEM_OPS
configuration to abstract such dependency so that other
weakly ordered architectures can reuse this infrastructure.
Signed-off-by: Jerin Jacob <jerin.jacob@caviumnetworks.com>
---
config/common_bsdapp | 5 +++++
config/common_linuxapp | 5 +++++
config/defconfig_arm64-armv8a-linuxapp-gcc | 1 +
config/defconfig_arm64-thunderx-linuxapp-gcc | 1 +
lib/librte_ring/rte_ring.h | 20 ++++++++++++++++++++
5 files changed, 32 insertions(+)
Comments
Do we need to have all these #ifdef, it looks messy, can you not define a macro that is defined based upon RTE_ARCH_STRONGLY_ORDERED_MEM_OP /Simon On 11/03/2015 03:52 PM, Jerin Jacob wrote: > rte_ring implementation needs explicit memory barrier > in weakly ordered architecture like ARM unlike > strongly ordered architecture like X86 > > Introducing RTE_ARCH_STRONGLY_ORDERED_MEM_OPS > configuration to abstract such dependency so that other > weakly ordered architectures can reuse this infrastructure. > > Signed-off-by: Jerin Jacob <jerin.jacob@caviumnetworks.com> > --- > config/common_bsdapp | 5 +++++ > config/common_linuxapp | 5 +++++ > config/defconfig_arm64-armv8a-linuxapp-gcc | 1 + > config/defconfig_arm64-thunderx-linuxapp-gcc | 1 + > lib/librte_ring/rte_ring.h | 20 ++++++++++++++++++++ > 5 files changed, 32 insertions(+) > > diff --git a/config/common_bsdapp b/config/common_bsdapp > index b37dcf4..c8d1f63 100644 > --- a/config/common_bsdapp > +++ b/config/common_bsdapp > @@ -79,6 +79,11 @@ CONFIG_RTE_FORCE_INTRINSICS=n > CONFIG_RTE_ARCH_STRICT_ALIGN=n > > # > +# Machine has strongly-ordered memory operations on normal memory like x86 > +# > +CONFIG_RTE_ARCH_STRONGLY_ORDERED_MEM_OPS=y > + > +# > # Compile to share library > # > CONFIG_RTE_BUILD_SHARED_LIB=n > diff --git a/config/common_linuxapp b/config/common_linuxapp > index 0de43d5..d040a74 100644 > --- a/config/common_linuxapp > +++ b/config/common_linuxapp > @@ -79,6 +79,11 @@ CONFIG_RTE_FORCE_INTRINSICS=n > CONFIG_RTE_ARCH_STRICT_ALIGN=n > > # > +# Machine has strongly-ordered memory operations on normal memory like x86 > +# > +CONFIG_RTE_ARCH_STRONGLY_ORDERED_MEM_OPS=y > + > +# > # Compile to share library > # > CONFIG_RTE_BUILD_SHARED_LIB=n > diff --git a/config/defconfig_arm64-armv8a-linuxapp-gcc b/config/defconfig_arm64-armv8a-linuxapp-gcc > index 6ea38a5..5289152 100644 > --- a/config/defconfig_arm64-armv8a-linuxapp-gcc > +++ b/config/defconfig_arm64-armv8a-linuxapp-gcc > @@ -37,6 +37,7 @@ CONFIG_RTE_ARCH="arm64" > CONFIG_RTE_ARCH_ARM64=y > CONFIG_RTE_ARCH_64=y > CONFIG_RTE_ARCH_ARM_NEON=y > +CONFIG_RTE_ARCH_STRONGLY_ORDERED_MEM_OPS=n > > CONFIG_RTE_FORCE_INTRINSICS=y > > diff --git a/config/defconfig_arm64-thunderx-linuxapp-gcc b/config/defconfig_arm64-thunderx-linuxapp-gcc > index e8fccc7..79fa9e6 100644 > --- a/config/defconfig_arm64-thunderx-linuxapp-gcc > +++ b/config/defconfig_arm64-thunderx-linuxapp-gcc > @@ -37,6 +37,7 @@ CONFIG_RTE_ARCH="arm64" > CONFIG_RTE_ARCH_ARM64=y > CONFIG_RTE_ARCH_64=y > CONFIG_RTE_ARCH_ARM_NEON=y > +CONFIG_RTE_ARCH_STRONGLY_ORDERED_MEM_OPS=n > > CONFIG_RTE_FORCE_INTRINSICS=y > > diff --git a/lib/librte_ring/rte_ring.h b/lib/librte_ring/rte_ring.h > index af68888..1ccd186 100644 > --- a/lib/librte_ring/rte_ring.h > +++ b/lib/librte_ring/rte_ring.h > @@ -457,7 +457,12 @@ __rte_ring_mp_do_enqueue(struct rte_ring *r, void * const *obj_table, > > /* write entries in ring */ > ENQUEUE_PTRS(); > + > +#ifdef RTE_ARCH_STRONGLY_ORDERED_MEM_OPS > rte_compiler_barrier(); > +#else > + rte_wmb(); > +#endif > > /* if we exceed the watermark */ > if (unlikely(((mask + 1) - free_entries + n) > r->prod.watermark)) { > @@ -552,7 +557,12 @@ __rte_ring_sp_do_enqueue(struct rte_ring *r, void * const *obj_table, > > /* write entries in ring */ > ENQUEUE_PTRS(); > + > +#ifdef RTE_ARCH_STRONGLY_ORDERED_MEM_OPS > rte_compiler_barrier(); > +#else > + rte_wmb(); > +#endif > > /* if we exceed the watermark */ > if (unlikely(((mask + 1) - free_entries + n) > r->prod.watermark)) { > @@ -643,7 +653,12 @@ __rte_ring_mc_do_dequeue(struct rte_ring *r, void **obj_table, > > /* copy in table */ > DEQUEUE_PTRS(); > + > +#ifdef RTE_ARCH_STRONGLY_ORDERED_MEM_OPS > rte_compiler_barrier(); > +#else > + rte_rmb(); > +#endif > > /* > * If there are other dequeues in progress that preceded us, > @@ -727,7 +742,12 @@ __rte_ring_sc_do_dequeue(struct rte_ring *r, void **obj_table, > > /* copy in table */ > DEQUEUE_PTRS(); > + > +#ifdef RTE_ARCH_STRONGLY_ORDERED_MEM_OPS > rte_compiler_barrier(); > +#else > + rte_rmb(); > +#endif > > __RING_STAT_ADD(r, deq_success, n); > r->cons.tail = cons_next;
> -----Original Message----- > From: dev [mailto:dev-bounces@dpdk.org] On Behalf Of Jerin Jacob > Sent: Tuesday, November 03, 2015 3:52 PM > To: dev@dpdk.org > Subject: [dpdk-dev] [RFC ][PATCH] Introduce RTE_ARCH_STRONGLY_ORDERED_MEM_OPS configuration parameter > > rte_ring implementation needs explicit memory barrier > in weakly ordered architecture like ARM unlike > strongly ordered architecture like X86 > > Introducing RTE_ARCH_STRONGLY_ORDERED_MEM_OPS > configuration to abstract such dependency so that other > weakly ordered architectures can reuse this infrastructure. Looks a bit clumsy. Please try to follow this suggestion instead: http://dpdk.org/ml/archives/dev/2015-October/025505.html Konstantin > > Signed-off-by: Jerin Jacob <jerin.jacob@caviumnetworks.com> > --- > config/common_bsdapp | 5 +++++ > config/common_linuxapp | 5 +++++ > config/defconfig_arm64-armv8a-linuxapp-gcc | 1 + > config/defconfig_arm64-thunderx-linuxapp-gcc | 1 + > lib/librte_ring/rte_ring.h | 20 ++++++++++++++++++++ > 5 files changed, 32 insertions(+) > > diff --git a/config/common_bsdapp b/config/common_bsdapp > index b37dcf4..c8d1f63 100644 > --- a/config/common_bsdapp > +++ b/config/common_bsdapp > @@ -79,6 +79,11 @@ CONFIG_RTE_FORCE_INTRINSICS=n > CONFIG_RTE_ARCH_STRICT_ALIGN=n > > # > +# Machine has strongly-ordered memory operations on normal memory like x86 > +# > +CONFIG_RTE_ARCH_STRONGLY_ORDERED_MEM_OPS=y > + > +# > # Compile to share library > # > CONFIG_RTE_BUILD_SHARED_LIB=n > diff --git a/config/common_linuxapp b/config/common_linuxapp > index 0de43d5..d040a74 100644 > --- a/config/common_linuxapp > +++ b/config/common_linuxapp > @@ -79,6 +79,11 @@ CONFIG_RTE_FORCE_INTRINSICS=n > CONFIG_RTE_ARCH_STRICT_ALIGN=n > > # > +# Machine has strongly-ordered memory operations on normal memory like x86 > +# > +CONFIG_RTE_ARCH_STRONGLY_ORDERED_MEM_OPS=y > + > +# > # Compile to share library > # > CONFIG_RTE_BUILD_SHARED_LIB=n > diff --git a/config/defconfig_arm64-armv8a-linuxapp-gcc b/config/defconfig_arm64-armv8a-linuxapp-gcc > index 6ea38a5..5289152 100644 > --- a/config/defconfig_arm64-armv8a-linuxapp-gcc > +++ b/config/defconfig_arm64-armv8a-linuxapp-gcc > @@ -37,6 +37,7 @@ CONFIG_RTE_ARCH="arm64" > CONFIG_RTE_ARCH_ARM64=y > CONFIG_RTE_ARCH_64=y > CONFIG_RTE_ARCH_ARM_NEON=y > +CONFIG_RTE_ARCH_STRONGLY_ORDERED_MEM_OPS=n > > CONFIG_RTE_FORCE_INTRINSICS=y > > diff --git a/config/defconfig_arm64-thunderx-linuxapp-gcc b/config/defconfig_arm64-thunderx-linuxapp-gcc > index e8fccc7..79fa9e6 100644 > --- a/config/defconfig_arm64-thunderx-linuxapp-gcc > +++ b/config/defconfig_arm64-thunderx-linuxapp-gcc > @@ -37,6 +37,7 @@ CONFIG_RTE_ARCH="arm64" > CONFIG_RTE_ARCH_ARM64=y > CONFIG_RTE_ARCH_64=y > CONFIG_RTE_ARCH_ARM_NEON=y > +CONFIG_RTE_ARCH_STRONGLY_ORDERED_MEM_OPS=n > > CONFIG_RTE_FORCE_INTRINSICS=y > > diff --git a/lib/librte_ring/rte_ring.h b/lib/librte_ring/rte_ring.h > index af68888..1ccd186 100644 > --- a/lib/librte_ring/rte_ring.h > +++ b/lib/librte_ring/rte_ring.h > @@ -457,7 +457,12 @@ __rte_ring_mp_do_enqueue(struct rte_ring *r, void * const *obj_table, > > /* write entries in ring */ > ENQUEUE_PTRS(); > + > +#ifdef RTE_ARCH_STRONGLY_ORDERED_MEM_OPS > rte_compiler_barrier(); > +#else > + rte_wmb(); > +#endif > > /* if we exceed the watermark */ > if (unlikely(((mask + 1) - free_entries + n) > r->prod.watermark)) { > @@ -552,7 +557,12 @@ __rte_ring_sp_do_enqueue(struct rte_ring *r, void * const *obj_table, > > /* write entries in ring */ > ENQUEUE_PTRS(); > + > +#ifdef RTE_ARCH_STRONGLY_ORDERED_MEM_OPS > rte_compiler_barrier(); > +#else > + rte_wmb(); > +#endif > > /* if we exceed the watermark */ > if (unlikely(((mask + 1) - free_entries + n) > r->prod.watermark)) { > @@ -643,7 +653,12 @@ __rte_ring_mc_do_dequeue(struct rte_ring *r, void **obj_table, > > /* copy in table */ > DEQUEUE_PTRS(); > + > +#ifdef RTE_ARCH_STRONGLY_ORDERED_MEM_OPS > rte_compiler_barrier(); > +#else > + rte_rmb(); > +#endif > > /* > * If there are other dequeues in progress that preceded us, > @@ -727,7 +742,12 @@ __rte_ring_sc_do_dequeue(struct rte_ring *r, void **obj_table, > > /* copy in table */ > DEQUEUE_PTRS(); > + > +#ifdef RTE_ARCH_STRONGLY_ORDERED_MEM_OPS > rte_compiler_barrier(); > +#else > + rte_rmb(); > +#endif > > __RING_STAT_ADD(r, deq_success, n); > r->cons.tail = cons_next; > -- > 2.1.0
On Tue, Nov 03, 2015 at 03:57:24PM +0000, Ananyev, Konstantin wrote: > > > > -----Original Message----- > > From: dev [mailto:dev-bounces@dpdk.org] On Behalf Of Jerin Jacob > > Sent: Tuesday, November 03, 2015 3:52 PM > > To: dev@dpdk.org > > Subject: [dpdk-dev] [RFC ][PATCH] Introduce RTE_ARCH_STRONGLY_ORDERED_MEM_OPS configuration parameter > > > > rte_ring implementation needs explicit memory barrier > > in weakly ordered architecture like ARM unlike > > strongly ordered architecture like X86 > > > > Introducing RTE_ARCH_STRONGLY_ORDERED_MEM_OPS > > configuration to abstract such dependency so that other > > weakly ordered architectures can reuse this infrastructure. > > Looks a bit clumsy. > Please try to follow this suggestion instead: > http://dpdk.org/ml/archives/dev/2015-October/025505.html Make sense. Do we agree on a macro that is defined based upon RTE_ARCH_STRONGLY_ORDERED_MEM_OP to remove clumsy #ifdef every where ? Jerin > > Konstantin > > > > > Signed-off-by: Jerin Jacob <jerin.jacob@caviumnetworks.com> > > --- > > config/common_bsdapp | 5 +++++ > > config/common_linuxapp | 5 +++++ > > config/defconfig_arm64-armv8a-linuxapp-gcc | 1 + > > config/defconfig_arm64-thunderx-linuxapp-gcc | 1 + > > lib/librte_ring/rte_ring.h | 20 ++++++++++++++++++++ > > 5 files changed, 32 insertions(+) > > > > diff --git a/config/common_bsdapp b/config/common_bsdapp > > index b37dcf4..c8d1f63 100644 > > --- a/config/common_bsdapp > > +++ b/config/common_bsdapp > > @@ -79,6 +79,11 @@ CONFIG_RTE_FORCE_INTRINSICS=n > > CONFIG_RTE_ARCH_STRICT_ALIGN=n > > > > # > > +# Machine has strongly-ordered memory operations on normal memory like x86 > > +# > > +CONFIG_RTE_ARCH_STRONGLY_ORDERED_MEM_OPS=y > > + > > +# > > # Compile to share library > > # > > CONFIG_RTE_BUILD_SHARED_LIB=n > > diff --git a/config/common_linuxapp b/config/common_linuxapp > > index 0de43d5..d040a74 100644 > > --- a/config/common_linuxapp > > +++ b/config/common_linuxapp > > @@ -79,6 +79,11 @@ CONFIG_RTE_FORCE_INTRINSICS=n > > CONFIG_RTE_ARCH_STRICT_ALIGN=n > > > > # > > +# Machine has strongly-ordered memory operations on normal memory like x86 > > +# > > +CONFIG_RTE_ARCH_STRONGLY_ORDERED_MEM_OPS=y > > + > > +# > > # Compile to share library > > # > > CONFIG_RTE_BUILD_SHARED_LIB=n > > diff --git a/config/defconfig_arm64-armv8a-linuxapp-gcc b/config/defconfig_arm64-armv8a-linuxapp-gcc > > index 6ea38a5..5289152 100644 > > --- a/config/defconfig_arm64-armv8a-linuxapp-gcc > > +++ b/config/defconfig_arm64-armv8a-linuxapp-gcc > > @@ -37,6 +37,7 @@ CONFIG_RTE_ARCH="arm64" > > CONFIG_RTE_ARCH_ARM64=y > > CONFIG_RTE_ARCH_64=y > > CONFIG_RTE_ARCH_ARM_NEON=y > > +CONFIG_RTE_ARCH_STRONGLY_ORDERED_MEM_OPS=n > > > > CONFIG_RTE_FORCE_INTRINSICS=y > > > > diff --git a/config/defconfig_arm64-thunderx-linuxapp-gcc b/config/defconfig_arm64-thunderx-linuxapp-gcc > > index e8fccc7..79fa9e6 100644 > > --- a/config/defconfig_arm64-thunderx-linuxapp-gcc > > +++ b/config/defconfig_arm64-thunderx-linuxapp-gcc > > @@ -37,6 +37,7 @@ CONFIG_RTE_ARCH="arm64" > > CONFIG_RTE_ARCH_ARM64=y > > CONFIG_RTE_ARCH_64=y > > CONFIG_RTE_ARCH_ARM_NEON=y > > +CONFIG_RTE_ARCH_STRONGLY_ORDERED_MEM_OPS=n > > > > CONFIG_RTE_FORCE_INTRINSICS=y > > > > diff --git a/lib/librte_ring/rte_ring.h b/lib/librte_ring/rte_ring.h > > index af68888..1ccd186 100644 > > --- a/lib/librte_ring/rte_ring.h > > +++ b/lib/librte_ring/rte_ring.h > > @@ -457,7 +457,12 @@ __rte_ring_mp_do_enqueue(struct rte_ring *r, void * const *obj_table, > > > > /* write entries in ring */ > > ENQUEUE_PTRS(); > > + > > +#ifdef RTE_ARCH_STRONGLY_ORDERED_MEM_OPS > > rte_compiler_barrier(); > > +#else > > + rte_wmb(); > > +#endif > > > > /* if we exceed the watermark */ > > if (unlikely(((mask + 1) - free_entries + n) > r->prod.watermark)) { > > @@ -552,7 +557,12 @@ __rte_ring_sp_do_enqueue(struct rte_ring *r, void * const *obj_table, > > > > /* write entries in ring */ > > ENQUEUE_PTRS(); > > + > > +#ifdef RTE_ARCH_STRONGLY_ORDERED_MEM_OPS > > rte_compiler_barrier(); > > +#else > > + rte_wmb(); > > +#endif > > > > /* if we exceed the watermark */ > > if (unlikely(((mask + 1) - free_entries + n) > r->prod.watermark)) { > > @@ -643,7 +653,12 @@ __rte_ring_mc_do_dequeue(struct rte_ring *r, void **obj_table, > > > > /* copy in table */ > > DEQUEUE_PTRS(); > > + > > +#ifdef RTE_ARCH_STRONGLY_ORDERED_MEM_OPS > > rte_compiler_barrier(); > > +#else > > + rte_rmb(); > > +#endif > > > > /* > > * If there are other dequeues in progress that preceded us, > > @@ -727,7 +742,12 @@ __rte_ring_sc_do_dequeue(struct rte_ring *r, void **obj_table, > > > > /* copy in table */ > > DEQUEUE_PTRS(); > > + > > +#ifdef RTE_ARCH_STRONGLY_ORDERED_MEM_OPS > > rte_compiler_barrier(); > > +#else > > + rte_rmb(); > > +#endif > > > > __RING_STAT_ADD(r, deq_success, n); > > r->cons.tail = cons_next; > > -- > > 2.1.0 >
> -----Original Message----- > From: dev [mailto:dev-bounces@dpdk.org] On Behalf Of Jerin Jacob > Sent: Tuesday, November 3, 2015 4:19 PM > To: Ananyev, Konstantin <konstantin.ananyev@intel.com> > Cc: dev@dpdk.org > Subject: Re: [dpdk-dev] [RFC ][PATCH] Introduce > RTE_ARCH_STRONGLY_ORDERED_MEM_OPS configuration parameter > > On Tue, Nov 03, 2015 at 03:57:24PM +0000, Ananyev, Konstantin wrote: > > > > > > > -----Original Message----- > > > From: dev [mailto:dev-bounces@dpdk.org] On Behalf Of Jerin Jacob > > > Sent: Tuesday, November 03, 2015 3:52 PM > > > To: dev@dpdk.org > > > Subject: [dpdk-dev] [RFC ][PATCH] Introduce > > > RTE_ARCH_STRONGLY_ORDERED_MEM_OPS configuration parameter > > > > > > rte_ring implementation needs explicit memory barrier in weakly > > > ordered architecture like ARM unlike strongly ordered architecture > > > like X86 > > > > > > Introducing RTE_ARCH_STRONGLY_ORDERED_MEM_OPS configuration to > > > abstract such dependency so that other weakly ordered architectures > > > can reuse this infrastructure. > > > > Looks a bit clumsy. > > Please try to follow this suggestion instead: > > http://dpdk.org/ml/archives/dev/2015-October/025505.html > > Make sense. Do we agree on a macro that is defined based upon > RTE_ARCH_STRONGLY_ORDERED_MEM_OP to remove clumsy #ifdef every where ? > > Jerin Yes to the single-defined barrier macro. However, for what controls it, is it really worthwhile defining a new RTE_ variable for it? Can we not base it on RTE_ARCH directly? /Bruce
> -----Original Message----- > From: Jerin Jacob [mailto:jerin.jacob@caviumnetworks.com] > Sent: Tuesday, November 03, 2015 4:19 PM > To: Ananyev, Konstantin > Cc: dev@dpdk.org > Subject: Re: [dpdk-dev] [RFC ][PATCH] Introduce RTE_ARCH_STRONGLY_ORDERED_MEM_OPS configuration parameter > > On Tue, Nov 03, 2015 at 03:57:24PM +0000, Ananyev, Konstantin wrote: > > > > > > > -----Original Message----- > > > From: dev [mailto:dev-bounces@dpdk.org] On Behalf Of Jerin Jacob > > > Sent: Tuesday, November 03, 2015 3:52 PM > > > To: dev@dpdk.org > > > Subject: [dpdk-dev] [RFC ][PATCH] Introduce RTE_ARCH_STRONGLY_ORDERED_MEM_OPS configuration parameter > > > > > > rte_ring implementation needs explicit memory barrier > > > in weakly ordered architecture like ARM unlike > > > strongly ordered architecture like X86 > > > > > > Introducing RTE_ARCH_STRONGLY_ORDERED_MEM_OPS > > > configuration to abstract such dependency so that other > > > weakly ordered architectures can reuse this infrastructure. > > > > Looks a bit clumsy. > > Please try to follow this suggestion instead: > > http://dpdk.org/ml/archives/dev/2015-October/025505.html > > Make sense. Do we agree on a macro that is defined based upon > RTE_ARCH_STRONGLY_ORDERED_MEM_OP to remove clumsy #ifdef every where ? Why do we need that macro at all? Why just not have architecture specific macro as was discussed in that thread? So for intel somewhere inside lib/librte_eal/common/include/arch/x86/rte_atomic.h it would be: #define rte_smp_wmb() rte_compiler_barrier() For arm inside lib/librte_eal/common/include/arch/x86/rte_atomic.h #define rte_smp_wmb() rte_wmb() And so on. I think it was already an attempt (not finished) to do similar stuff for ppc: http://dpdk.org/dev/patchwork/patch/5884/ Konstantin > > Jerin > > > > > Konstantin > > > > > > > > Signed-off-by: Jerin Jacob <jerin.jacob@caviumnetworks.com> > > > --- > > > config/common_bsdapp | 5 +++++ > > > config/common_linuxapp | 5 +++++ > > > config/defconfig_arm64-armv8a-linuxapp-gcc | 1 + > > > config/defconfig_arm64-thunderx-linuxapp-gcc | 1 + > > > lib/librte_ring/rte_ring.h | 20 ++++++++++++++++++++ > > > 5 files changed, 32 insertions(+) > > > > > > diff --git a/config/common_bsdapp b/config/common_bsdapp > > > index b37dcf4..c8d1f63 100644 > > > --- a/config/common_bsdapp > > > +++ b/config/common_bsdapp > > > @@ -79,6 +79,11 @@ CONFIG_RTE_FORCE_INTRINSICS=n > > > CONFIG_RTE_ARCH_STRICT_ALIGN=n > > > > > > # > > > +# Machine has strongly-ordered memory operations on normal memory like x86 > > > +# > > > +CONFIG_RTE_ARCH_STRONGLY_ORDERED_MEM_OPS=y > > > + > > > +# > > > # Compile to share library > > > # > > > CONFIG_RTE_BUILD_SHARED_LIB=n > > > diff --git a/config/common_linuxapp b/config/common_linuxapp > > > index 0de43d5..d040a74 100644 > > > --- a/config/common_linuxapp > > > +++ b/config/common_linuxapp > > > @@ -79,6 +79,11 @@ CONFIG_RTE_FORCE_INTRINSICS=n > > > CONFIG_RTE_ARCH_STRICT_ALIGN=n > > > > > > # > > > +# Machine has strongly-ordered memory operations on normal memory like x86 > > > +# > > > +CONFIG_RTE_ARCH_STRONGLY_ORDERED_MEM_OPS=y > > > + > > > +# > > > # Compile to share library > > > # > > > CONFIG_RTE_BUILD_SHARED_LIB=n > > > diff --git a/config/defconfig_arm64-armv8a-linuxapp-gcc b/config/defconfig_arm64-armv8a-linuxapp-gcc > > > index 6ea38a5..5289152 100644 > > > --- a/config/defconfig_arm64-armv8a-linuxapp-gcc > > > +++ b/config/defconfig_arm64-armv8a-linuxapp-gcc > > > @@ -37,6 +37,7 @@ CONFIG_RTE_ARCH="arm64" > > > CONFIG_RTE_ARCH_ARM64=y > > > CONFIG_RTE_ARCH_64=y > > > CONFIG_RTE_ARCH_ARM_NEON=y > > > +CONFIG_RTE_ARCH_STRONGLY_ORDERED_MEM_OPS=n > > > > > > CONFIG_RTE_FORCE_INTRINSICS=y > > > > > > diff --git a/config/defconfig_arm64-thunderx-linuxapp-gcc b/config/defconfig_arm64-thunderx-linuxapp-gcc > > > index e8fccc7..79fa9e6 100644 > > > --- a/config/defconfig_arm64-thunderx-linuxapp-gcc > > > +++ b/config/defconfig_arm64-thunderx-linuxapp-gcc > > > @@ -37,6 +37,7 @@ CONFIG_RTE_ARCH="arm64" > > > CONFIG_RTE_ARCH_ARM64=y > > > CONFIG_RTE_ARCH_64=y > > > CONFIG_RTE_ARCH_ARM_NEON=y > > > +CONFIG_RTE_ARCH_STRONGLY_ORDERED_MEM_OPS=n > > > > > > CONFIG_RTE_FORCE_INTRINSICS=y > > > > > > diff --git a/lib/librte_ring/rte_ring.h b/lib/librte_ring/rte_ring.h > > > index af68888..1ccd186 100644 > > > --- a/lib/librte_ring/rte_ring.h > > > +++ b/lib/librte_ring/rte_ring.h > > > @@ -457,7 +457,12 @@ __rte_ring_mp_do_enqueue(struct rte_ring *r, void * const *obj_table, > > > > > > /* write entries in ring */ > > > ENQUEUE_PTRS(); > > > + > > > +#ifdef RTE_ARCH_STRONGLY_ORDERED_MEM_OPS > > > rte_compiler_barrier(); > > > +#else > > > + rte_wmb(); > > > +#endif > > > > > > /* if we exceed the watermark */ > > > if (unlikely(((mask + 1) - free_entries + n) > r->prod.watermark)) { > > > @@ -552,7 +557,12 @@ __rte_ring_sp_do_enqueue(struct rte_ring *r, void * const *obj_table, > > > > > > /* write entries in ring */ > > > ENQUEUE_PTRS(); > > > + > > > +#ifdef RTE_ARCH_STRONGLY_ORDERED_MEM_OPS > > > rte_compiler_barrier(); > > > +#else > > > + rte_wmb(); > > > +#endif > > > > > > /* if we exceed the watermark */ > > > if (unlikely(((mask + 1) - free_entries + n) > r->prod.watermark)) { > > > @@ -643,7 +653,12 @@ __rte_ring_mc_do_dequeue(struct rte_ring *r, void **obj_table, > > > > > > /* copy in table */ > > > DEQUEUE_PTRS(); > > > + > > > +#ifdef RTE_ARCH_STRONGLY_ORDERED_MEM_OPS > > > rte_compiler_barrier(); > > > +#else > > > + rte_rmb(); > > > +#endif > > > > > > /* > > > * If there are other dequeues in progress that preceded us, > > > @@ -727,7 +742,12 @@ __rte_ring_sc_do_dequeue(struct rte_ring *r, void **obj_table, > > > > > > /* copy in table */ > > > DEQUEUE_PTRS(); > > > + > > > +#ifdef RTE_ARCH_STRONGLY_ORDERED_MEM_OPS > > > rte_compiler_barrier(); > > > +#else > > > + rte_rmb(); > > > +#endif > > > > > > __RING_STAT_ADD(r, deq_success, n); > > > r->cons.tail = cons_next; > > > -- > > > 2.1.0 > >
On Tue, Nov 03, 2015 at 04:28:00PM +0000, Ananyev, Konstantin wrote: > > > > -----Original Message----- > > From: Jerin Jacob [mailto:jerin.jacob@caviumnetworks.com] > > Sent: Tuesday, November 03, 2015 4:19 PM > > To: Ananyev, Konstantin > > Cc: dev@dpdk.org > > Subject: Re: [dpdk-dev] [RFC ][PATCH] Introduce RTE_ARCH_STRONGLY_ORDERED_MEM_OPS configuration parameter > > > > On Tue, Nov 03, 2015 at 03:57:24PM +0000, Ananyev, Konstantin wrote: > > > > > > > > > > -----Original Message----- > > > > From: dev [mailto:dev-bounces@dpdk.org] On Behalf Of Jerin Jacob > > > > Sent: Tuesday, November 03, 2015 3:52 PM > > > > To: dev@dpdk.org > > > > Subject: [dpdk-dev] [RFC ][PATCH] Introduce RTE_ARCH_STRONGLY_ORDERED_MEM_OPS configuration parameter > > > > > > > > rte_ring implementation needs explicit memory barrier > > > > in weakly ordered architecture like ARM unlike > > > > strongly ordered architecture like X86 > > > > > > > > Introducing RTE_ARCH_STRONGLY_ORDERED_MEM_OPS > > > > configuration to abstract such dependency so that other > > > > weakly ordered architectures can reuse this infrastructure. > > > > > > Looks a bit clumsy. > > > Please try to follow this suggestion instead: > > > http://dpdk.org/ml/archives/dev/2015-October/025505.html > > > > Make sense. Do we agree on a macro that is defined based upon > > RTE_ARCH_STRONGLY_ORDERED_MEM_OP to remove clumsy #ifdef every where ? > > Why do we need that macro at all? > Why just not have architecture specific macro as was discussed in that thread? > > So for intel somewhere inside > lib/librte_eal/common/include/arch/x86/rte_atomic.h > > it would be: > > #define rte_smp_wmb() rte_compiler_barrier() > > For arm inside lib/librte_eal/common/include/arch/x86/rte_atomic.h > > #define rte_smp_wmb() rte_wmb() I am not sure about the other architecture but in armv8 device memory (typically mapped through NIC PCIe BAR space) are strongly ordered. So there is one more dimension to the equation(normal memory or device memory). IMO rte_smp_wmb() -> rte_wmb() mapping to deal with device memory may not be correct on arm64 ? Thoughts ? > > And so on. > > I think it was already an attempt (not finished) to do similar stuff for ppc: > http://dpdk.org/dev/patchwork/patch/5884/ > > Konstantin > > > > > Jerin > > > > > > > > Konstantin > > > > > > > > > > > Signed-off-by: Jerin Jacob <jerin.jacob@caviumnetworks.com> > > > > --- > > > > config/common_bsdapp | 5 +++++ > > > > config/common_linuxapp | 5 +++++ > > > > config/defconfig_arm64-armv8a-linuxapp-gcc | 1 + > > > > config/defconfig_arm64-thunderx-linuxapp-gcc | 1 + > > > > lib/librte_ring/rte_ring.h | 20 ++++++++++++++++++++ > > > > 5 files changed, 32 insertions(+) > > > > > > > > diff --git a/config/common_bsdapp b/config/common_bsdapp > > > > index b37dcf4..c8d1f63 100644 > > > > --- a/config/common_bsdapp > > > > +++ b/config/common_bsdapp > > > > @@ -79,6 +79,11 @@ CONFIG_RTE_FORCE_INTRINSICS=n > > > > CONFIG_RTE_ARCH_STRICT_ALIGN=n > > > > > > > > # > > > > +# Machine has strongly-ordered memory operations on normal memory like x86 > > > > +# > > > > +CONFIG_RTE_ARCH_STRONGLY_ORDERED_MEM_OPS=y > > > > + > > > > +# > > > > # Compile to share library > > > > # > > > > CONFIG_RTE_BUILD_SHARED_LIB=n > > > > diff --git a/config/common_linuxapp b/config/common_linuxapp > > > > index 0de43d5..d040a74 100644 > > > > --- a/config/common_linuxapp > > > > +++ b/config/common_linuxapp > > > > @@ -79,6 +79,11 @@ CONFIG_RTE_FORCE_INTRINSICS=n > > > > CONFIG_RTE_ARCH_STRICT_ALIGN=n > > > > > > > > # > > > > +# Machine has strongly-ordered memory operations on normal memory like x86 > > > > +# > > > > +CONFIG_RTE_ARCH_STRONGLY_ORDERED_MEM_OPS=y > > > > + > > > > +# > > > > # Compile to share library > > > > # > > > > CONFIG_RTE_BUILD_SHARED_LIB=n > > > > diff --git a/config/defconfig_arm64-armv8a-linuxapp-gcc b/config/defconfig_arm64-armv8a-linuxapp-gcc > > > > index 6ea38a5..5289152 100644 > > > > --- a/config/defconfig_arm64-armv8a-linuxapp-gcc > > > > +++ b/config/defconfig_arm64-armv8a-linuxapp-gcc > > > > @@ -37,6 +37,7 @@ CONFIG_RTE_ARCH="arm64" > > > > CONFIG_RTE_ARCH_ARM64=y > > > > CONFIG_RTE_ARCH_64=y > > > > CONFIG_RTE_ARCH_ARM_NEON=y > > > > +CONFIG_RTE_ARCH_STRONGLY_ORDERED_MEM_OPS=n > > > > > > > > CONFIG_RTE_FORCE_INTRINSICS=y > > > > > > > > diff --git a/config/defconfig_arm64-thunderx-linuxapp-gcc b/config/defconfig_arm64-thunderx-linuxapp-gcc > > > > index e8fccc7..79fa9e6 100644 > > > > --- a/config/defconfig_arm64-thunderx-linuxapp-gcc > > > > +++ b/config/defconfig_arm64-thunderx-linuxapp-gcc > > > > @@ -37,6 +37,7 @@ CONFIG_RTE_ARCH="arm64" > > > > CONFIG_RTE_ARCH_ARM64=y > > > > CONFIG_RTE_ARCH_64=y > > > > CONFIG_RTE_ARCH_ARM_NEON=y > > > > +CONFIG_RTE_ARCH_STRONGLY_ORDERED_MEM_OPS=n > > > > > > > > CONFIG_RTE_FORCE_INTRINSICS=y > > > > > > > > diff --git a/lib/librte_ring/rte_ring.h b/lib/librte_ring/rte_ring.h > > > > index af68888..1ccd186 100644 > > > > --- a/lib/librte_ring/rte_ring.h > > > > +++ b/lib/librte_ring/rte_ring.h > > > > @@ -457,7 +457,12 @@ __rte_ring_mp_do_enqueue(struct rte_ring *r, void * const *obj_table, > > > > > > > > /* write entries in ring */ > > > > ENQUEUE_PTRS(); > > > > + > > > > +#ifdef RTE_ARCH_STRONGLY_ORDERED_MEM_OPS > > > > rte_compiler_barrier(); > > > > +#else > > > > + rte_wmb(); > > > > +#endif > > > > > > > > /* if we exceed the watermark */ > > > > if (unlikely(((mask + 1) - free_entries + n) > r->prod.watermark)) { > > > > @@ -552,7 +557,12 @@ __rte_ring_sp_do_enqueue(struct rte_ring *r, void * const *obj_table, > > > > > > > > /* write entries in ring */ > > > > ENQUEUE_PTRS(); > > > > + > > > > +#ifdef RTE_ARCH_STRONGLY_ORDERED_MEM_OPS > > > > rte_compiler_barrier(); > > > > +#else > > > > + rte_wmb(); > > > > +#endif > > > > > > > > /* if we exceed the watermark */ > > > > if (unlikely(((mask + 1) - free_entries + n) > r->prod.watermark)) { > > > > @@ -643,7 +653,12 @@ __rte_ring_mc_do_dequeue(struct rte_ring *r, void **obj_table, > > > > > > > > /* copy in table */ > > > > DEQUEUE_PTRS(); > > > > + > > > > +#ifdef RTE_ARCH_STRONGLY_ORDERED_MEM_OPS > > > > rte_compiler_barrier(); > > > > +#else > > > > + rte_rmb(); > > > > +#endif > > > > > > > > /* > > > > * If there are other dequeues in progress that preceded us, > > > > @@ -727,7 +742,12 @@ __rte_ring_sc_do_dequeue(struct rte_ring *r, void **obj_table, > > > > > > > > /* copy in table */ > > > > DEQUEUE_PTRS(); > > > > + > > > > +#ifdef RTE_ARCH_STRONGLY_ORDERED_MEM_OPS > > > > rte_compiler_barrier(); > > > > +#else > > > > + rte_rmb(); > > > > +#endif > > > > > > > > __RING_STAT_ADD(r, deq_success, n); > > > > r->cons.tail = cons_next; > > > > -- > > > > 2.1.0 > > >
> -----Original Message----- > From: dev [mailto:dev-bounces@dpdk.org] On Behalf Of Jerin Jacob > Sent: Tuesday, November 3, 2015 4:53 PM > To: Ananyev, Konstantin <konstantin.ananyev@intel.com> > Cc: dev@dpdk.org > Subject: Re: [dpdk-dev] [RFC ][PATCH] Introduce > RTE_ARCH_STRONGLY_ORDERED_MEM_OPS configuration parameter > > On Tue, Nov 03, 2015 at 04:28:00PM +0000, Ananyev, Konstantin wrote: > > > > > > > -----Original Message----- > > > From: Jerin Jacob [mailto:jerin.jacob@caviumnetworks.com] > > > Sent: Tuesday, November 03, 2015 4:19 PM > > > To: Ananyev, Konstantin > > > Cc: dev@dpdk.org > > > Subject: Re: [dpdk-dev] [RFC ][PATCH] Introduce > > > RTE_ARCH_STRONGLY_ORDERED_MEM_OPS configuration parameter > > > > > > On Tue, Nov 03, 2015 at 03:57:24PM +0000, Ananyev, Konstantin wrote: > > > > > > > > > > > > > -----Original Message----- > > > > > From: dev [mailto:dev-bounces@dpdk.org] On Behalf Of Jerin Jacob > > > > > Sent: Tuesday, November 03, 2015 3:52 PM > > > > > To: dev@dpdk.org > > > > > Subject: [dpdk-dev] [RFC ][PATCH] Introduce > > > > > RTE_ARCH_STRONGLY_ORDERED_MEM_OPS configuration parameter > > > > > > > > > > rte_ring implementation needs explicit memory barrier in weakly > > > > > ordered architecture like ARM unlike strongly ordered > > > > > architecture like X86 > > > > > > > > > > Introducing RTE_ARCH_STRONGLY_ORDERED_MEM_OPS configuration to > > > > > abstract such dependency so that other weakly ordered > > > > > architectures can reuse this infrastructure. > > > > > > > > Looks a bit clumsy. > > > > Please try to follow this suggestion instead: > > > > http://dpdk.org/ml/archives/dev/2015-October/025505.html > > > > > > Make sense. Do we agree on a macro that is defined based upon > > > RTE_ARCH_STRONGLY_ORDERED_MEM_OP to remove clumsy #ifdef every where ? > > > > Why do we need that macro at all? > > Why just not have architecture specific macro as was discussed in that > thread? > > > > So for intel somewhere inside > > lib/librte_eal/common/include/arch/x86/rte_atomic.h > > > > it would be: > > > > #define rte_smp_wmb() rte_compiler_barrier() > > > > For arm inside lib/librte_eal/common/include/arch/x86/rte_atomic.h > > > > #define rte_smp_wmb() rte_wmb() > > I am not sure about the other architecture but in armv8 device memory > (typically mapped through NIC PCIe BAR space) are strongly ordered. > So there is one more dimension to the equation(normal memory or device > memory). > IMO rte_smp_wmb() -> rte_wmb() mapping to deal with device memory may not > be correct on arm64 ? > > Thoughts ? > In cases like that I don't think barriers are needed on any platform so the proposed scheme will work fine. It's up the driver writer to know about when they are writing to device BARs or not. /Bruce
> -----Original Message----- > From: Jerin Jacob [mailto:jerin.jacob@caviumnetworks.com] > Sent: Tuesday, November 03, 2015 4:53 PM > To: Ananyev, Konstantin > Cc: dev@dpdk.org > Subject: Re: [dpdk-dev] [RFC ][PATCH] Introduce RTE_ARCH_STRONGLY_ORDERED_MEM_OPS configuration parameter > > On Tue, Nov 03, 2015 at 04:28:00PM +0000, Ananyev, Konstantin wrote: > > > > > > > -----Original Message----- > > > From: Jerin Jacob [mailto:jerin.jacob@caviumnetworks.com] > > > Sent: Tuesday, November 03, 2015 4:19 PM > > > To: Ananyev, Konstantin > > > Cc: dev@dpdk.org > > > Subject: Re: [dpdk-dev] [RFC ][PATCH] Introduce RTE_ARCH_STRONGLY_ORDERED_MEM_OPS configuration parameter > > > > > > On Tue, Nov 03, 2015 at 03:57:24PM +0000, Ananyev, Konstantin wrote: > > > > > > > > > > > > > -----Original Message----- > > > > > From: dev [mailto:dev-bounces@dpdk.org] On Behalf Of Jerin Jacob > > > > > Sent: Tuesday, November 03, 2015 3:52 PM > > > > > To: dev@dpdk.org > > > > > Subject: [dpdk-dev] [RFC ][PATCH] Introduce RTE_ARCH_STRONGLY_ORDERED_MEM_OPS configuration parameter > > > > > > > > > > rte_ring implementation needs explicit memory barrier > > > > > in weakly ordered architecture like ARM unlike > > > > > strongly ordered architecture like X86 > > > > > > > > > > Introducing RTE_ARCH_STRONGLY_ORDERED_MEM_OPS > > > > > configuration to abstract such dependency so that other > > > > > weakly ordered architectures can reuse this infrastructure. > > > > > > > > Looks a bit clumsy. > > > > Please try to follow this suggestion instead: > > > > http://dpdk.org/ml/archives/dev/2015-October/025505.html > > > > > > Make sense. Do we agree on a macro that is defined based upon > > > RTE_ARCH_STRONGLY_ORDERED_MEM_OP to remove clumsy #ifdef every where ? > > > > Why do we need that macro at all? > > Why just not have architecture specific macro as was discussed in that thread? > > > > So for intel somewhere inside > > lib/librte_eal/common/include/arch/x86/rte_atomic.h > > > > it would be: > > > > #define rte_smp_wmb() rte_compiler_barrier() > > > > For arm inside lib/librte_eal/common/include/arch/x86/rte_atomic.h > > > > #define rte_smp_wmb() rte_wmb() > > I am not sure about the other architecture but in armv8 device memory > (typically mapped through NIC PCIe BAR space) are strongly ordered. > So there is one more dimension to the equation(normal memory or device > memory). > IMO rte_smp_wmb() -> rte_wmb() mapping to deal with device memory may > not be correct on arm64 ? I thought we are talking now for multi-processor case no? For that would be: rte_smp_... set of macros. Similar to what linux guys have. Konstantin > > Thoughts ? > > > > > And so on. > > > > I think it was already an attempt (not finished) to do similar stuff for ppc: > > http://dpdk.org/dev/patchwork/patch/5884/ > > > > Konstantin > > > > > > > > Jerin > > > > > > > > > > > Konstantin > > > > > > > > > > > > > > Signed-off-by: Jerin Jacob <jerin.jacob@caviumnetworks.com> > > > > > --- > > > > > config/common_bsdapp | 5 +++++ > > > > > config/common_linuxapp | 5 +++++ > > > > > config/defconfig_arm64-armv8a-linuxapp-gcc | 1 + > > > > > config/defconfig_arm64-thunderx-linuxapp-gcc | 1 + > > > > > lib/librte_ring/rte_ring.h | 20 ++++++++++++++++++++ > > > > > 5 files changed, 32 insertions(+) > > > > > > > > > > diff --git a/config/common_bsdapp b/config/common_bsdapp > > > > > index b37dcf4..c8d1f63 100644 > > > > > --- a/config/common_bsdapp > > > > > +++ b/config/common_bsdapp > > > > > @@ -79,6 +79,11 @@ CONFIG_RTE_FORCE_INTRINSICS=n > > > > > CONFIG_RTE_ARCH_STRICT_ALIGN=n > > > > > > > > > > # > > > > > +# Machine has strongly-ordered memory operations on normal memory like x86 > > > > > +# > > > > > +CONFIG_RTE_ARCH_STRONGLY_ORDERED_MEM_OPS=y > > > > > + > > > > > +# > > > > > # Compile to share library > > > > > # > > > > > CONFIG_RTE_BUILD_SHARED_LIB=n > > > > > diff --git a/config/common_linuxapp b/config/common_linuxapp > > > > > index 0de43d5..d040a74 100644 > > > > > --- a/config/common_linuxapp > > > > > +++ b/config/common_linuxapp > > > > > @@ -79,6 +79,11 @@ CONFIG_RTE_FORCE_INTRINSICS=n > > > > > CONFIG_RTE_ARCH_STRICT_ALIGN=n > > > > > > > > > > # > > > > > +# Machine has strongly-ordered memory operations on normal memory like x86 > > > > > +# > > > > > +CONFIG_RTE_ARCH_STRONGLY_ORDERED_MEM_OPS=y > > > > > + > > > > > +# > > > > > # Compile to share library > > > > > # > > > > > CONFIG_RTE_BUILD_SHARED_LIB=n > > > > > diff --git a/config/defconfig_arm64-armv8a-linuxapp-gcc b/config/defconfig_arm64-armv8a-linuxapp-gcc > > > > > index 6ea38a5..5289152 100644 > > > > > --- a/config/defconfig_arm64-armv8a-linuxapp-gcc > > > > > +++ b/config/defconfig_arm64-armv8a-linuxapp-gcc > > > > > @@ -37,6 +37,7 @@ CONFIG_RTE_ARCH="arm64" > > > > > CONFIG_RTE_ARCH_ARM64=y > > > > > CONFIG_RTE_ARCH_64=y > > > > > CONFIG_RTE_ARCH_ARM_NEON=y > > > > > +CONFIG_RTE_ARCH_STRONGLY_ORDERED_MEM_OPS=n > > > > > > > > > > CONFIG_RTE_FORCE_INTRINSICS=y > > > > > > > > > > diff --git a/config/defconfig_arm64-thunderx-linuxapp-gcc b/config/defconfig_arm64-thunderx-linuxapp-gcc > > > > > index e8fccc7..79fa9e6 100644 > > > > > --- a/config/defconfig_arm64-thunderx-linuxapp-gcc > > > > > +++ b/config/defconfig_arm64-thunderx-linuxapp-gcc > > > > > @@ -37,6 +37,7 @@ CONFIG_RTE_ARCH="arm64" > > > > > CONFIG_RTE_ARCH_ARM64=y > > > > > CONFIG_RTE_ARCH_64=y > > > > > CONFIG_RTE_ARCH_ARM_NEON=y > > > > > +CONFIG_RTE_ARCH_STRONGLY_ORDERED_MEM_OPS=n > > > > > > > > > > CONFIG_RTE_FORCE_INTRINSICS=y > > > > > > > > > > diff --git a/lib/librte_ring/rte_ring.h b/lib/librte_ring/rte_ring.h > > > > > index af68888..1ccd186 100644 > > > > > --- a/lib/librte_ring/rte_ring.h > > > > > +++ b/lib/librte_ring/rte_ring.h > > > > > @@ -457,7 +457,12 @@ __rte_ring_mp_do_enqueue(struct rte_ring *r, void * const *obj_table, > > > > > > > > > > /* write entries in ring */ > > > > > ENQUEUE_PTRS(); > > > > > + > > > > > +#ifdef RTE_ARCH_STRONGLY_ORDERED_MEM_OPS > > > > > rte_compiler_barrier(); > > > > > +#else > > > > > + rte_wmb(); > > > > > +#endif > > > > > > > > > > /* if we exceed the watermark */ > > > > > if (unlikely(((mask + 1) - free_entries + n) > r->prod.watermark)) { > > > > > @@ -552,7 +557,12 @@ __rte_ring_sp_do_enqueue(struct rte_ring *r, void * const *obj_table, > > > > > > > > > > /* write entries in ring */ > > > > > ENQUEUE_PTRS(); > > > > > + > > > > > +#ifdef RTE_ARCH_STRONGLY_ORDERED_MEM_OPS > > > > > rte_compiler_barrier(); > > > > > +#else > > > > > + rte_wmb(); > > > > > +#endif > > > > > > > > > > /* if we exceed the watermark */ > > > > > if (unlikely(((mask + 1) - free_entries + n) > r->prod.watermark)) { > > > > > @@ -643,7 +653,12 @@ __rte_ring_mc_do_dequeue(struct rte_ring *r, void **obj_table, > > > > > > > > > > /* copy in table */ > > > > > DEQUEUE_PTRS(); > > > > > + > > > > > +#ifdef RTE_ARCH_STRONGLY_ORDERED_MEM_OPS > > > > > rte_compiler_barrier(); > > > > > +#else > > > > > + rte_rmb(); > > > > > +#endif > > > > > > > > > > /* > > > > > * If there are other dequeues in progress that preceded us, > > > > > @@ -727,7 +742,12 @@ __rte_ring_sc_do_dequeue(struct rte_ring *r, void **obj_table, > > > > > > > > > > /* copy in table */ > > > > > DEQUEUE_PTRS(); > > > > > + > > > > > +#ifdef RTE_ARCH_STRONGLY_ORDERED_MEM_OPS > > > > > rte_compiler_barrier(); > > > > > +#else > > > > > + rte_rmb(); > > > > > +#endif > > > > > > > > > > __RING_STAT_ADD(r, deq_success, n); > > > > > r->cons.tail = cons_next; > > > > > -- > > > > > 2.1.0 > > > >
On Tue, Nov 03, 2015 at 05:12:21PM +0000, Ananyev, Konstantin wrote: > > > > -----Original Message----- > > From: Jerin Jacob [mailto:jerin.jacob@caviumnetworks.com] > > Sent: Tuesday, November 03, 2015 4:53 PM > > To: Ananyev, Konstantin > > Cc: dev@dpdk.org > > Subject: Re: [dpdk-dev] [RFC ][PATCH] Introduce RTE_ARCH_STRONGLY_ORDERED_MEM_OPS configuration parameter > > > > On Tue, Nov 03, 2015 at 04:28:00PM +0000, Ananyev, Konstantin wrote: > > > > > > > > > > -----Original Message----- > > > > From: Jerin Jacob [mailto:jerin.jacob@caviumnetworks.com] > > > > Sent: Tuesday, November 03, 2015 4:19 PM > > > > To: Ananyev, Konstantin > > > > Cc: dev@dpdk.org > > > > Subject: Re: [dpdk-dev] [RFC ][PATCH] Introduce RTE_ARCH_STRONGLY_ORDERED_MEM_OPS configuration parameter > > > > > > > > On Tue, Nov 03, 2015 at 03:57:24PM +0000, Ananyev, Konstantin wrote: > > > > > > > > > > > > > > > > -----Original Message----- > > > > > > From: dev [mailto:dev-bounces@dpdk.org] On Behalf Of Jerin Jacob > > > > > > Sent: Tuesday, November 03, 2015 3:52 PM > > > > > > To: dev@dpdk.org > > > > > > Subject: [dpdk-dev] [RFC ][PATCH] Introduce RTE_ARCH_STRONGLY_ORDERED_MEM_OPS configuration parameter > > > > > > > > > > > > rte_ring implementation needs explicit memory barrier > > > > > > in weakly ordered architecture like ARM unlike > > > > > > strongly ordered architecture like X86 > > > > > > > > > > > > Introducing RTE_ARCH_STRONGLY_ORDERED_MEM_OPS > > > > > > configuration to abstract such dependency so that other > > > > > > weakly ordered architectures can reuse this infrastructure. > > > > > > > > > > Looks a bit clumsy. > > > > > Please try to follow this suggestion instead: > > > > > http://dpdk.org/ml/archives/dev/2015-October/025505.html > > > > > > > > Make sense. Do we agree on a macro that is defined based upon > > > > RTE_ARCH_STRONGLY_ORDERED_MEM_OP to remove clumsy #ifdef every where ? > > > > > > Why do we need that macro at all? > > > Why just not have architecture specific macro as was discussed in that thread? > > > > > > So for intel somewhere inside > > > lib/librte_eal/common/include/arch/x86/rte_atomic.h > > > > > > it would be: > > > > > > #define rte_smp_wmb() rte_compiler_barrier() > > > > > > For arm inside lib/librte_eal/common/include/arch/x86/rte_atomic.h > > > > > > #define rte_smp_wmb() rte_wmb() > > > > I am not sure about the other architecture but in armv8 device memory > > (typically mapped through NIC PCIe BAR space) are strongly ordered. > > So there is one more dimension to the equation(normal memory or device > > memory). > > IMO rte_smp_wmb() -> rte_wmb() mapping to deal with device memory may > > not be correct on arm64 ? > > I thought we are talking now for multi-processor case no? > For that would be: rte_smp_... set of macros. > Similar to what linux guys have. make sense. I will send out RFC patch for the defintion and implementation of rte_smp_wb(),rte_smp_wmb(), and rte_smp_rmb() Jerin > Konstantin > > > > > Thoughts ? > > > > > > > > > > > > And so on. > > > > > > I think it was already an attempt (not finished) to do similar stuff for ppc: > > > http://dpdk.org/dev/patchwork/patch/5884/ > > > > > > Konstantin > > > > > > > > > > > Jerin > > > > > > > > > > > > > > Konstantin > > > > > > > > > > > > > > > > > Signed-off-by: Jerin Jacob <jerin.jacob@caviumnetworks.com> > > > > > > --- > > > > > > config/common_bsdapp | 5 +++++ > > > > > > config/common_linuxapp | 5 +++++ > > > > > > config/defconfig_arm64-armv8a-linuxapp-gcc | 1 + > > > > > > config/defconfig_arm64-thunderx-linuxapp-gcc | 1 + > > > > > > lib/librte_ring/rte_ring.h | 20 ++++++++++++++++++++ > > > > > > 5 files changed, 32 insertions(+) > > > > > > > > > > > > diff --git a/config/common_bsdapp b/config/common_bsdapp > > > > > > index b37dcf4..c8d1f63 100644 > > > > > > --- a/config/common_bsdapp > > > > > > +++ b/config/common_bsdapp > > > > > > @@ -79,6 +79,11 @@ CONFIG_RTE_FORCE_INTRINSICS=n > > > > > > CONFIG_RTE_ARCH_STRICT_ALIGN=n > > > > > > > > > > > > # > > > > > > +# Machine has strongly-ordered memory operations on normal memory like x86 > > > > > > +# > > > > > > +CONFIG_RTE_ARCH_STRONGLY_ORDERED_MEM_OPS=y > > > > > > + > > > > > > +# > > > > > > # Compile to share library > > > > > > # > > > > > > CONFIG_RTE_BUILD_SHARED_LIB=n > > > > > > diff --git a/config/common_linuxapp b/config/common_linuxapp > > > > > > index 0de43d5..d040a74 100644 > > > > > > --- a/config/common_linuxapp > > > > > > +++ b/config/common_linuxapp > > > > > > @@ -79,6 +79,11 @@ CONFIG_RTE_FORCE_INTRINSICS=n > > > > > > CONFIG_RTE_ARCH_STRICT_ALIGN=n > > > > > > > > > > > > # > > > > > > +# Machine has strongly-ordered memory operations on normal memory like x86 > > > > > > +# > > > > > > +CONFIG_RTE_ARCH_STRONGLY_ORDERED_MEM_OPS=y > > > > > > + > > > > > > +# > > > > > > # Compile to share library > > > > > > # > > > > > > CONFIG_RTE_BUILD_SHARED_LIB=n > > > > > > diff --git a/config/defconfig_arm64-armv8a-linuxapp-gcc b/config/defconfig_arm64-armv8a-linuxapp-gcc > > > > > > index 6ea38a5..5289152 100644 > > > > > > --- a/config/defconfig_arm64-armv8a-linuxapp-gcc > > > > > > +++ b/config/defconfig_arm64-armv8a-linuxapp-gcc > > > > > > @@ -37,6 +37,7 @@ CONFIG_RTE_ARCH="arm64" > > > > > > CONFIG_RTE_ARCH_ARM64=y > > > > > > CONFIG_RTE_ARCH_64=y > > > > > > CONFIG_RTE_ARCH_ARM_NEON=y > > > > > > +CONFIG_RTE_ARCH_STRONGLY_ORDERED_MEM_OPS=n > > > > > > > > > > > > CONFIG_RTE_FORCE_INTRINSICS=y > > > > > > > > > > > > diff --git a/config/defconfig_arm64-thunderx-linuxapp-gcc b/config/defconfig_arm64-thunderx-linuxapp-gcc > > > > > > index e8fccc7..79fa9e6 100644 > > > > > > --- a/config/defconfig_arm64-thunderx-linuxapp-gcc > > > > > > +++ b/config/defconfig_arm64-thunderx-linuxapp-gcc > > > > > > @@ -37,6 +37,7 @@ CONFIG_RTE_ARCH="arm64" > > > > > > CONFIG_RTE_ARCH_ARM64=y > > > > > > CONFIG_RTE_ARCH_64=y > > > > > > CONFIG_RTE_ARCH_ARM_NEON=y > > > > > > +CONFIG_RTE_ARCH_STRONGLY_ORDERED_MEM_OPS=n > > > > > > > > > > > > CONFIG_RTE_FORCE_INTRINSICS=y > > > > > > > > > > > > diff --git a/lib/librte_ring/rte_ring.h b/lib/librte_ring/rte_ring.h > > > > > > index af68888..1ccd186 100644 > > > > > > --- a/lib/librte_ring/rte_ring.h > > > > > > +++ b/lib/librte_ring/rte_ring.h > > > > > > @@ -457,7 +457,12 @@ __rte_ring_mp_do_enqueue(struct rte_ring *r, void * const *obj_table, > > > > > > > > > > > > /* write entries in ring */ > > > > > > ENQUEUE_PTRS(); > > > > > > + > > > > > > +#ifdef RTE_ARCH_STRONGLY_ORDERED_MEM_OPS > > > > > > rte_compiler_barrier(); > > > > > > +#else > > > > > > + rte_wmb(); > > > > > > +#endif > > > > > > > > > > > > /* if we exceed the watermark */ > > > > > > if (unlikely(((mask + 1) - free_entries + n) > r->prod.watermark)) { > > > > > > @@ -552,7 +557,12 @@ __rte_ring_sp_do_enqueue(struct rte_ring *r, void * const *obj_table, > > > > > > > > > > > > /* write entries in ring */ > > > > > > ENQUEUE_PTRS(); > > > > > > + > > > > > > +#ifdef RTE_ARCH_STRONGLY_ORDERED_MEM_OPS > > > > > > rte_compiler_barrier(); > > > > > > +#else > > > > > > + rte_wmb(); > > > > > > +#endif > > > > > > > > > > > > /* if we exceed the watermark */ > > > > > > if (unlikely(((mask + 1) - free_entries + n) > r->prod.watermark)) { > > > > > > @@ -643,7 +653,12 @@ __rte_ring_mc_do_dequeue(struct rte_ring *r, void **obj_table, > > > > > > > > > > > > /* copy in table */ > > > > > > DEQUEUE_PTRS(); > > > > > > + > > > > > > +#ifdef RTE_ARCH_STRONGLY_ORDERED_MEM_OPS > > > > > > rte_compiler_barrier(); > > > > > > +#else > > > > > > + rte_rmb(); > > > > > > +#endif > > > > > > > > > > > > /* > > > > > > * If there are other dequeues in progress that preceded us, > > > > > > @@ -727,7 +742,12 @@ __rte_ring_sc_do_dequeue(struct rte_ring *r, void **obj_table, > > > > > > > > > > > > /* copy in table */ > > > > > > DEQUEUE_PTRS(); > > > > > > + > > > > > > +#ifdef RTE_ARCH_STRONGLY_ORDERED_MEM_OPS > > > > > > rte_compiler_barrier(); > > > > > > +#else > > > > > > + rte_rmb(); > > > > > > +#endif > > > > > > > > > > > > __RING_STAT_ADD(r, deq_success, n); > > > > > > r->cons.tail = cons_next; > > > > > > -- > > > > > > 2.1.0 > > > > >
diff --git a/config/common_bsdapp b/config/common_bsdapp index b37dcf4..c8d1f63 100644 --- a/config/common_bsdapp +++ b/config/common_bsdapp @@ -79,6 +79,11 @@ CONFIG_RTE_FORCE_INTRINSICS=n CONFIG_RTE_ARCH_STRICT_ALIGN=n # +# Machine has strongly-ordered memory operations on normal memory like x86 +# +CONFIG_RTE_ARCH_STRONGLY_ORDERED_MEM_OPS=y + +# # Compile to share library # CONFIG_RTE_BUILD_SHARED_LIB=n diff --git a/config/common_linuxapp b/config/common_linuxapp index 0de43d5..d040a74 100644 --- a/config/common_linuxapp +++ b/config/common_linuxapp @@ -79,6 +79,11 @@ CONFIG_RTE_FORCE_INTRINSICS=n CONFIG_RTE_ARCH_STRICT_ALIGN=n # +# Machine has strongly-ordered memory operations on normal memory like x86 +# +CONFIG_RTE_ARCH_STRONGLY_ORDERED_MEM_OPS=y + +# # Compile to share library # CONFIG_RTE_BUILD_SHARED_LIB=n diff --git a/config/defconfig_arm64-armv8a-linuxapp-gcc b/config/defconfig_arm64-armv8a-linuxapp-gcc index 6ea38a5..5289152 100644 --- a/config/defconfig_arm64-armv8a-linuxapp-gcc +++ b/config/defconfig_arm64-armv8a-linuxapp-gcc @@ -37,6 +37,7 @@ CONFIG_RTE_ARCH="arm64" CONFIG_RTE_ARCH_ARM64=y CONFIG_RTE_ARCH_64=y CONFIG_RTE_ARCH_ARM_NEON=y +CONFIG_RTE_ARCH_STRONGLY_ORDERED_MEM_OPS=n CONFIG_RTE_FORCE_INTRINSICS=y diff --git a/config/defconfig_arm64-thunderx-linuxapp-gcc b/config/defconfig_arm64-thunderx-linuxapp-gcc index e8fccc7..79fa9e6 100644 --- a/config/defconfig_arm64-thunderx-linuxapp-gcc +++ b/config/defconfig_arm64-thunderx-linuxapp-gcc @@ -37,6 +37,7 @@ CONFIG_RTE_ARCH="arm64" CONFIG_RTE_ARCH_ARM64=y CONFIG_RTE_ARCH_64=y CONFIG_RTE_ARCH_ARM_NEON=y +CONFIG_RTE_ARCH_STRONGLY_ORDERED_MEM_OPS=n CONFIG_RTE_FORCE_INTRINSICS=y diff --git a/lib/librte_ring/rte_ring.h b/lib/librte_ring/rte_ring.h index af68888..1ccd186 100644 --- a/lib/librte_ring/rte_ring.h +++ b/lib/librte_ring/rte_ring.h @@ -457,7 +457,12 @@ __rte_ring_mp_do_enqueue(struct rte_ring *r, void * const *obj_table, /* write entries in ring */ ENQUEUE_PTRS(); + +#ifdef RTE_ARCH_STRONGLY_ORDERED_MEM_OPS rte_compiler_barrier(); +#else + rte_wmb(); +#endif /* if we exceed the watermark */ if (unlikely(((mask + 1) - free_entries + n) > r->prod.watermark)) { @@ -552,7 +557,12 @@ __rte_ring_sp_do_enqueue(struct rte_ring *r, void * const *obj_table, /* write entries in ring */ ENQUEUE_PTRS(); + +#ifdef RTE_ARCH_STRONGLY_ORDERED_MEM_OPS rte_compiler_barrier(); +#else + rte_wmb(); +#endif /* if we exceed the watermark */ if (unlikely(((mask + 1) - free_entries + n) > r->prod.watermark)) { @@ -643,7 +653,12 @@ __rte_ring_mc_do_dequeue(struct rte_ring *r, void **obj_table, /* copy in table */ DEQUEUE_PTRS(); + +#ifdef RTE_ARCH_STRONGLY_ORDERED_MEM_OPS rte_compiler_barrier(); +#else + rte_rmb(); +#endif /* * If there are other dequeues in progress that preceded us, @@ -727,7 +742,12 @@ __rte_ring_sc_do_dequeue(struct rte_ring *r, void **obj_table, /* copy in table */ DEQUEUE_PTRS(); + +#ifdef RTE_ARCH_STRONGLY_ORDERED_MEM_OPS rte_compiler_barrier(); +#else + rte_rmb(); +#endif __RING_STAT_ADD(r, deq_success, n); r->cons.tail = cons_next;