From patchwork Mon Nov 2 23:47:25 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jan Viktorin X-Patchwork-Id: 8558 Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [IPv6:::1]) by dpdk.org (Postfix) with ESMTP id 2283E91CA; Tue, 3 Nov 2015 00:50:32 +0100 (CET) Received: from wes1-so1.wedos.net (wes1-so1.wedos.net [46.28.106.15]) by dpdk.org (Postfix) with ESMTP id 904F48E7D for ; Tue, 3 Nov 2015 00:50:22 +0100 (CET) Received: from pcviktorin.fit.vutbr.cz (pcviktorin.fit.vutbr.cz [147.229.13.147]) by wes1-so1.wedos.net (Postfix) with ESMTPSA id 3nqWFp29Snz31m; Tue, 3 Nov 2015 00:50:22 +0100 (CET) From: Jan Viktorin To: david.marchand@6wind.com, David Hunt , Thomas Monjalon , Jerin Jacob Date: Tue, 3 Nov 2015 00:47:25 +0100 Message-Id: <1446508048-16744-13-git-send-email-viktorin@rehivetech.com> X-Mailer: git-send-email 2.6.2 In-Reply-To: <1446508048-16744-1-git-send-email-viktorin@rehivetech.com> References: <1446508048-16744-1-git-send-email-viktorin@rehivetech.com> Cc: dev@dpdk.org Subject: [dpdk-dev] [PATCH v6 12/15] eal/arm: add very incomplete rte_vect X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" This patch does not map x86 SIMD operations to the ARM ones. It just fills the necessary gap between the platforms to enable compilation of libraries LPM (includes rte_vect.h, lpm_test needs those SIMD functions) and ACL (includes rte_vect.h). Signed-off-by: Jan Viktorin --- v4: checkpatch reports warning for the new typedef --- lib/librte_eal/common/include/arch/arm/rte_vect.h | 84 +++++++++++++++++++++++ 1 file changed, 84 insertions(+) create mode 100644 lib/librte_eal/common/include/arch/arm/rte_vect.h diff --git a/lib/librte_eal/common/include/arch/arm/rte_vect.h b/lib/librte_eal/common/include/arch/arm/rte_vect.h new file mode 100644 index 0000000..7d5de97 --- /dev/null +++ b/lib/librte_eal/common/include/arch/arm/rte_vect.h @@ -0,0 +1,84 @@ +/*- + * BSD LICENSE + * + * Copyright(c) 2015 RehiveTech. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of RehiveTech nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _RTE_VECT_ARM_H_ +#define _RTE_VECT_ARM_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define XMM_SIZE 16 +#define XMM_MASK (XMM_MASK - 1) + +typedef struct { + union uint128 { + uint8_t uint8[16]; + uint32_t uint32[4]; + } val; +} __m128i; + +static inline __m128i +_mm_set_epi32(uint32_t v0, uint32_t v1, uint32_t v2, uint32_t v3) +{ + __m128i res; + + res.val.uint32[0] = v0; + res.val.uint32[1] = v1; + res.val.uint32[2] = v2; + res.val.uint32[3] = v3; + return res; +} + +static inline __m128i +_mm_loadu_si128(__m128i *v) +{ + __m128i res; + + res = *v; + return res; +} + +static inline __m128i +_mm_load_si128(__m128i *v) +{ + __m128i res; + + res = *v; + return res; +} + +#ifdef __cplusplus +} +#endif + +#endif