From patchwork Sat Oct 31 15:57:23 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jingjing Wu X-Patchwork-Id: 8494 Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [IPv6:::1]) by dpdk.org (Postfix) with ESMTP id 2B9F68D9F; Sat, 31 Oct 2015 16:57:47 +0100 (CET) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by dpdk.org (Postfix) with ESMTP id 067075A4F for ; Sat, 31 Oct 2015 16:57:41 +0100 (CET) Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga102.jf.intel.com with ESMTP; 31 Oct 2015 08:57:40 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.20,224,1444719600"; d="scan'208";a="823856815" Received: from shvmail01.sh.intel.com ([10.239.29.42]) by fmsmga001.fm.intel.com with ESMTP; 31 Oct 2015 08:57:40 -0700 Received: from shecgisg004.sh.intel.com (shecgisg004.sh.intel.com [10.239.29.89]) by shvmail01.sh.intel.com with ESMTP id t9VFvcdu032711; Sat, 31 Oct 2015 23:57:38 +0800 Received: from shecgisg004.sh.intel.com (localhost [127.0.0.1]) by shecgisg004.sh.intel.com (8.13.6/8.13.6/SuSE Linux 0.8) with ESMTP id t9VFvYEK029324; Sat, 31 Oct 2015 23:57:37 +0800 Received: (from wujingji@localhost) by shecgisg004.sh.intel.com (8.13.6/8.13.6/Submit) id t9VFvYcZ029320; Sat, 31 Oct 2015 23:57:34 +0800 From: Jingjing Wu To: dev@dpdk.org Date: Sat, 31 Oct 2015 23:57:23 +0800 Message-Id: <1446307051-29283-2-git-send-email-jingjing.wu@intel.com> X-Mailer: git-send-email 1.7.4.1 In-Reply-To: <1446307051-29283-1-git-send-email-jingjing.wu@intel.com> References: <1446108827-7907-1-git-send-email-jingjing.wu@intel.com> <1446307051-29283-1-git-send-email-jingjing.wu@intel.com> Subject: [dpdk-dev] [PATCH v3 1/9] ethdev: rename dcb_queue to dcb_tc in dcb config struct X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Signed-off-by: Jingjing Wu --- app/test-pmd/testpmd.c | 8 ++++---- doc/guides/rel_notes/release_2_2.rst | 4 ++++ drivers/net/ixgbe/ixgbe_rxtx.c | 10 +++++----- examples/vmdq_dcb/main.c | 4 ++-- lib/librte_ether/rte_ethdev.h | 14 +++++++------- 5 files changed, 22 insertions(+), 18 deletions(-) diff --git a/app/test-pmd/testpmd.c b/app/test-pmd/testpmd.c index 3cd3cd0..4c6aec6 100644 --- a/app/test-pmd/testpmd.c +++ b/app/test-pmd/testpmd.c @@ -1878,8 +1878,8 @@ get_eth_dcb_conf(struct rte_eth_conf *eth_conf, struct dcb_config *dcb_conf) vmdq_rx_conf.pool_map[i].pools = 1 << (i % vmdq_rx_conf.nb_queue_pools); } for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) { - vmdq_rx_conf.dcb_queue[i] = i; - vmdq_tx_conf.dcb_queue[i] = i; + vmdq_rx_conf.dcb_tc[i] = i; + vmdq_tx_conf.dcb_tc[i] = i; } /*set DCB mode of RX and TX of multiple queues*/ @@ -1909,8 +1909,8 @@ get_eth_dcb_conf(struct rte_eth_conf *eth_conf, struct dcb_config *dcb_conf) tx_conf.nb_tcs = dcb_conf->num_tcs; for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++){ - rx_conf.dcb_queue[i] = i; - tx_conf.dcb_queue[i] = i; + rx_conf.dcb_tc[i] = i; + tx_conf.dcb_tc[i] = i; } eth_conf->rxmode.mq_mode = ETH_MQ_RX_DCB; eth_conf->txmode.mq_mode = ETH_MQ_TX_DCB; diff --git a/doc/guides/rel_notes/release_2_2.rst b/doc/guides/rel_notes/release_2_2.rst index 116162e..1857e1d 100644 --- a/doc/guides/rel_notes/release_2_2.rst +++ b/doc/guides/rel_notes/release_2_2.rst @@ -138,6 +138,10 @@ API Changes * The devargs union field virtual is renamed to virt for C++ compatibility. +* The dcb_queue is renamed to dcb_tc in following dcb configuration + structures: rte_eth_dcb_rx_conf, rte_eth_vmdq_dcb_tx_conf, + rte_eth_dcb_tx_conf, rte_eth_vmdq_dcb_conf. + ABI Changes ----------- diff --git a/drivers/net/ixgbe/ixgbe_rxtx.c b/drivers/net/ixgbe/ixgbe_rxtx.c index 1158562..6a62d67 100644 --- a/drivers/net/ixgbe/ixgbe_rxtx.c +++ b/drivers/net/ixgbe/ixgbe_rxtx.c @@ -2928,7 +2928,7 @@ ixgbe_vmdq_dcb_configure(struct rte_eth_dev *dev) * mapping is done with 3 bits per priority, * so shift by i*3 each time */ - queue_mapping |= ((cfg->dcb_queue[i] & 0x07) << (i * 3)); + queue_mapping |= ((cfg->dcb_tc[i] & 0x07) << (i * 3)); IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, queue_mapping); @@ -3063,7 +3063,7 @@ ixgbe_vmdq_dcb_rx_config(struct rte_eth_dev *dev, } /* User Priority to Traffic Class mapping */ for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) { - j = vmdq_rx_conf->dcb_queue[i]; + j = vmdq_rx_conf->dcb_tc[i]; tc = &dcb_config->tc_config[j]; tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = (uint8_t)(1 << j); @@ -3091,7 +3091,7 @@ ixgbe_dcb_vt_tx_config(struct rte_eth_dev *dev, /* User Priority to Traffic Class mapping */ for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) { - j = vmdq_tx_conf->dcb_queue[i]; + j = vmdq_tx_conf->dcb_tc[i]; tc = &dcb_config->tc_config[j]; tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = (uint8_t)(1 << j); @@ -3113,7 +3113,7 @@ ixgbe_dcb_rx_config(struct rte_eth_dev *dev, /* User Priority to Traffic Class mapping */ for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) { - j = rx_conf->dcb_queue[i]; + j = rx_conf->dcb_tc[i]; tc = &dcb_config->tc_config[j]; tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = (uint8_t)(1 << j); @@ -3134,7 +3134,7 @@ ixgbe_dcb_tx_config(struct rte_eth_dev *dev, /* User Priority to Traffic Class mapping */ for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) { - j = tx_conf->dcb_queue[i]; + j = tx_conf->dcb_tc[i]; tc = &dcb_config->tc_config[j]; tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = (uint8_t)(1 << j); diff --git a/examples/vmdq_dcb/main.c b/examples/vmdq_dcb/main.c index c31c2ce..b90ac28 100644 --- a/examples/vmdq_dcb/main.c +++ b/examples/vmdq_dcb/main.c @@ -107,7 +107,7 @@ static const struct rte_eth_conf vmdq_dcb_conf_default = { .default_pool = 0, .nb_pool_maps = 0, .pool_map = {{0, 0},}, - .dcb_queue = {0}, + .dcb_tc = {0}, }, }, }; @@ -144,7 +144,7 @@ get_eth_conf(struct rte_eth_conf *eth_conf, enum rte_eth_nb_pools num_pools) conf.pool_map[i].pools = 1 << (i % num_pools); } for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++){ - conf.dcb_queue[i] = (uint8_t)(i % (NUM_QUEUES/num_pools)); + conf.dcb_tc[i] = (uint8_t)(i % (NUM_QUEUES/num_pools)); } (void)(rte_memcpy(eth_conf, &vmdq_dcb_conf_default, sizeof(*eth_conf))); (void)(rte_memcpy(ð_conf->rx_adv_conf.vmdq_dcb_conf, &conf, diff --git a/lib/librte_ether/rte_ethdev.h b/lib/librte_ether/rte_ethdev.h index 8a8c82b..377da6a 100644 --- a/lib/librte_ether/rte_ethdev.h +++ b/lib/librte_ether/rte_ethdev.h @@ -543,20 +543,20 @@ enum rte_eth_nb_pools { /* This structure may be extended in future. */ struct rte_eth_dcb_rx_conf { enum rte_eth_nb_tcs nb_tcs; /**< Possible DCB TCs, 4 or 8 TCs */ - uint8_t dcb_queue[ETH_DCB_NUM_USER_PRIORITIES]; - /**< Possible DCB queue,4 or 8. */ + /** Traffic class each UP mapped to. */ + uint8_t dcb_tc[ETH_DCB_NUM_USER_PRIORITIES]; }; struct rte_eth_vmdq_dcb_tx_conf { enum rte_eth_nb_pools nb_queue_pools; /**< With DCB, 16 or 32 pools. */ - uint8_t dcb_queue[ETH_DCB_NUM_USER_PRIORITIES]; - /**< Possible DCB queue,4 or 8. */ + /** Traffic class each UP mapped to. */ + uint8_t dcb_tc[ETH_DCB_NUM_USER_PRIORITIES]; }; struct rte_eth_dcb_tx_conf { enum rte_eth_nb_tcs nb_tcs; /**< Possible DCB TCs, 4 or 8 TCs. */ - uint8_t dcb_queue[ETH_DCB_NUM_USER_PRIORITIES]; - /**< Possible DCB queue,4 or 8. */ + /** Traffic class each UP mapped to. */ + uint8_t dcb_tc[ETH_DCB_NUM_USER_PRIORITIES]; }; struct rte_eth_vmdq_tx_conf { @@ -583,7 +583,7 @@ struct rte_eth_vmdq_dcb_conf { uint16_t vlan_id; /**< The vlan id of the received frame */ uint64_t pools; /**< Bitmask of pools for packet rx */ } pool_map[ETH_VMDQ_MAX_VLAN_FILTERS]; /**< VMDq vlan pool maps. */ - uint8_t dcb_queue[ETH_DCB_NUM_USER_PRIORITIES]; + uint8_t dcb_tc[ETH_DCB_NUM_USER_PRIORITIES]; /**< Selects a queue in a pool */ };