[dpdk-dev,v3,01/17] mk: Introduce ARMv7 architecture
Commit Message
From: Vlastimil Kosar <kosar@rehivetech.com>
Make DPDK run on ARMv7-A architecture. This patch assumes
ARM Cortex-A9. However, it is known to be working on Cortex-A7
and Cortex-A15.
Signed-off-by: Vlastimil Kosar <kosar@rehivetech.com>
Signed-off-by: Jan Viktorin <viktorin@rehivetech.com>
---
v1 -> v2:
* the -mtune parameter of GCC is configurable now
* the -mfpu=neon can be turned off
v2 -> v3: XMM_SIZE is defined in rte_vect.h in a following patch
---
config/defconfig_arm-armv7-a-linuxapp-gcc | 75 +++++++++++++++++++++++++++++++
mk/arch/arm/rte.vars.mk | 39 ++++++++++++++++
mk/machine/armv7-a/rte.vars.mk | 67 +++++++++++++++++++++++++++
3 files changed, 181 insertions(+)
create mode 100644 config/defconfig_arm-armv7-a-linuxapp-gcc
create mode 100644 mk/arch/arm/rte.vars.mk
create mode 100644 mk/machine/armv7-a/rte.vars.mk
Comments
Hello Jan,
On Tue, Oct 27, 2015 at 8:13 PM, Jan Viktorin <viktorin@rehivetech.com>
wrote:
>
> diff --git a/config/defconfig_arm-armv7-a-linuxapp-gcc
> b/config/defconfig_arm-armv7-a-linuxapp-gcc
> new file mode 100644
> index 0000000..5a778cf
> --- /dev/null
> +++ b/config/defconfig_arm-armv7-a-linuxapp-gcc
> +
> +# avoids using i686/x86_64 SIMD instructions, nothing for ARM
> +CONFIG_RTE_BITMAP_OPTIMIZATIONS=0
>
(<unrelated>yet another build flag which has to disappear, and bitmap
header should be moved from librte_sched to eal with arch-specific
implementations when applicable</unrelated>)
Well, I am a bit confused by this comment.
For me, gcc provides ctzll builtins.
https://gcc.gnu.org/onlinedocs/gcc/Other-Builtins.html
And with your patchset applied, it builds fine with
RTE_BITMAP_OPTIMIZATIONS enabled using gcc 4.7.3 for arm on ubuntu 14.04.
Is there a dependency on gcc version ?
+# PCI is usually not used on ARM
> +CONFIG_RTE_EAL_IGB_UIO=n
>
Not sure "usually not used" is a good reason to disable something.
Is there a real issue on arm with igb_uio code (compilation, pci accesses) ?
Thanks.
On Wed, 28 Oct 2015 11:09:21 +0100
David Marchand <david.marchand@6wind.com> wrote:
> Hello Jan,
>
> On Tue, Oct 27, 2015 at 8:13 PM, Jan Viktorin <viktorin@rehivetech.com>
> wrote:
>
> >
> > diff --git a/config/defconfig_arm-armv7-a-linuxapp-gcc
> > b/config/defconfig_arm-armv7-a-linuxapp-gcc
> > new file mode 100644
> > index 0000000..5a778cf
> > --- /dev/null
> > +++ b/config/defconfig_arm-armv7-a-linuxapp-gcc
> > +
> > +# avoids using i686/x86_64 SIMD instructions, nothing for ARM
> > +CONFIG_RTE_BITMAP_OPTIMIZATIONS=0
> >
>
> (<unrelated>yet another build flag which has to disappear, and bitmap
> header should be moved from librte_sched to eal with arch-specific
> implementations when applicable</unrelated>)
>
> Well, I am a bit confused by this comment.
> For me, gcc provides ctzll builtins.
> https://gcc.gnu.org/onlinedocs/gcc/Other-Builtins.html
>
> And with your patchset applied, it builds fine with
> RTE_BITMAP_OPTIMIZATIONS enabled using gcc 4.7.3 for arm on ubuntu 14.04.
> Is there a dependency on gcc version ?
It seems, there is no need for this. I will remove it. DPDK compiles
well.
>
>
> +# PCI is usually not used on ARM
> > +CONFIG_RTE_EAL_IGB_UIO=n
> >
>
> Not sure "usually not used" is a good reason to disable something.
> Is there a real issue on arm with igb_uio code (compilation, pci accesses) ?
>
Well, it requires to set some options in Linux Kernel (at least PCI
support) which are usually disabled by the in-kernel *arm*_defconfigs.
Moreover, it seems I cannot enable it for some ARM architectures (I've
tried Altera SoC FPGA). That's because you hardly find an ARMv7 system
with a PCI bus. I suppose that if somebody _really_ needs this, she would
enable it by hand.
At the moment, it breaks my common builds... The driver is mostly
useless on ARMv7 and just takes space in the filesystem.
>
> Thanks.
>
Regards
Jan
On Wed, Oct 28, 2015 at 11:56 AM, Jan Viktorin <viktorin@rehivetech.com>
wrote:
> On Wed, 28 Oct 2015 11:09:21 +0100
> David Marchand <david.marchand@6wind.com> wrote:
>
> > +# PCI is usually not used on ARM
> > > +CONFIG_RTE_EAL_IGB_UIO=n
> > >
> >
> > Not sure "usually not used" is a good reason to disable something.
> > Is there a real issue on arm with igb_uio code (compilation, pci
> accesses) ?
> >
>
> Well, it requires to set some options in Linux Kernel (at least PCI
> support) which are usually disabled by the in-kernel *arm*_defconfigs.
> Moreover, it seems I cannot enable it for some ARM architectures (I've
> tried Altera SoC FPGA). That's because you hardly find an ARMv7 system
> with a PCI bus. I suppose that if somebody _really_ needs this, she would
> enable it by hand.
>
> At the moment, it breaks my common builds... The driver is mostly
> useless on ARMv7 and just takes space in the filesystem.
>
>
Ok, well, at the moment, you seem to be the only user :-)
Let's see what other people say.
On 28/10/2015 10:56, Jan Viktorin wrote:
> On Wed, 28 Oct 2015 11:09:21 +0100
> David Marchand <david.marchand@6wind.com> wrote:
>
>> Hello Jan,
>>
>> On Tue, Oct 27, 2015 at 8:13 PM, Jan Viktorin <viktorin@rehivetech.com>
>> wrote:
>>
>> +# PCI is usually not used on ARM
>>> +CONFIG_RTE_EAL_IGB_UIO=n
>>>
>>
>> Not sure "usually not used" is a good reason to disable something.
>> Is there a real issue on arm with igb_uio code (compilation, pci accesses) ?
>>
>
> Well, it requires to set some options in Linux Kernel (at least PCI
> support) which are usually disabled by the in-kernel *arm*_defconfigs.
> Moreover, it seems I cannot enable it for some ARM architectures (I've
> tried Altera SoC FPGA). That's because you hardly find an ARMv7 system
> with a PCI bus. I suppose that if somebody _really_ needs this, she would
> enable it by hand.
>
> At the moment, it breaks my common builds... The driver is mostly
> useless on ARMv7 and just takes space in the filesystem.
I have an ARMv8 board here that I've built a new kernel for the purposes
of an ARMv8 port, and it took quite a while to get the PCI
functionality all working, including implementing a fix to the kernel
PCI driver to expose the mmap resources in sysfs properly. But after
that, igb_uio compiles fine (on the ARMv8 patch) and works with a
Niantic to pass traffic between ports.
If the majority of ARMv7 boards don't have a PCI bus, then I'd suggest
leaving igb_uio disabled. Those few boards with PCI will most likely
have a correctly kernel (and source) ready to go, so enabling igb_uio
for them will be easy, but disabling seems a more sensible default for
the majority of ARMv7 users.
Rgds,
Dave.
new file mode 100644
@@ -0,0 +1,75 @@
+# BSD LICENSE
+#
+# Copyright (C) 2015 RehiveTech. All right reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+#
+# * Redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer.
+# * Redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in
+# the documentation and/or other materials provided with the
+# distribution.
+# * Neither the name of RehiveTech nor the names of its
+# contributors may be used to endorse or promote products derived
+# from this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+#include "common_linuxapp"
+
+CONFIG_RTE_MACHINE="armv7-a"
+
+CONFIG_RTE_ARCH="arm"
+CONFIG_RTE_ARCH_ARM=y
+CONFIG_RTE_ARCH_ARMv7=y
+CONFIG_RTE_ARCH_ARM_TUNE="cortex-a9"
+CONFIG_RTE_ARCH_ARM_NEON=y
+
+CONFIG_RTE_TOOLCHAIN="gcc"
+CONFIG_RTE_TOOLCHAIN_GCC=y
+
+# ARM doesn't have support for vmware TSC map
+CONFIG_RTE_LIBRTE_EAL_VMWARE_TSC_MAP_SUPPORT=n
+
+# avoids using i686/x86_64 SIMD instructions, nothing for ARM
+CONFIG_RTE_BITMAP_OPTIMIZATIONS=0
+
+# KNI is not supported on 32-bit
+CONFIG_RTE_LIBRTE_KNI=n
+
+# PCI is usually not used on ARM
+CONFIG_RTE_EAL_IGB_UIO=n
+
+# fails to compile on ARM
+CONFIG_RTE_LIBRTE_ACL=n
+CONFIG_RTE_LIBRTE_LPM=n
+
+# cannot use those on ARM
+CONFIG_RTE_KNI_KMOD=n
+CONFIG_RTE_LIBRTE_EM_PMD=n
+CONFIG_RTE_LIBRTE_IGB_PMD=n
+CONFIG_RTE_LIBRTE_CXGBE_PMD=n
+CONFIG_RTE_LIBRTE_E1000_PMD=n
+CONFIG_RTE_LIBRTE_ENIC_PMD=n
+CONFIG_RTE_LIBRTE_FM10K_PMD=n
+CONFIG_RTE_LIBRTE_I40E_PMD=n
+CONFIG_RTE_LIBRTE_IXGBE_PMD=n
+CONFIG_RTE_LIBRTE_MLX4_PMD=n
+CONFIG_RTE_LIBRTE_MPIPE_PMD=n
+CONFIG_RTE_LIBRTE_VIRTIO_PMD=n
+CONFIG_RTE_LIBRTE_VMXNET3_PMD=n
+CONFIG_RTE_LIBRTE_PMD_XENVIRT=n
+CONFIG_RTE_LIBRTE_PMD_BNX2X=n
new file mode 100644
@@ -0,0 +1,39 @@
+# BSD LICENSE
+#
+# Copyright (C) 2015 RehiveTech. All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+#
+# * Redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer.
+# * Redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in
+# the documentation and/or other materials provided with the
+# distribution.
+# * Neither the name of RehiveTech nor the names of its
+# contributors may be used to endorse or promote products derived
+# from this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+
+ARCH ?= arm
+CROSS ?=
+
+CPU_CFLAGS ?= -marm -DRTE_CACHE_LINE_SIZE=64 -munaligned-access
+CPU_LDFLAGS ?=
+CPU_ASFLAGS ?= -felf
+
+export ARCH CROSS CPU_CFLAGS CPU_LDFLAGS CPU_ASFLAGS
new file mode 100644
@@ -0,0 +1,67 @@
+# BSD LICENSE
+#
+# Copyright (C) 2015 RehiveTech. All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+#
+# * Redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer.
+# * Redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in
+# the documentation and/or other materials provided with the
+# distribution.
+# * Neither the name of RehiveTech nor the names of its
+# contributors may be used to endorse or promote products derived
+# from this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+#
+# machine:
+#
+# - can define ARCH variable (overridden by cmdline value)
+# - can define CROSS variable (overridden by cmdline value)
+# - define MACHINE_CFLAGS variable (overridden by cmdline value)
+# - define MACHINE_LDFLAGS variable (overridden by cmdline value)
+# - define MACHINE_ASFLAGS variable (overridden by cmdline value)
+# - can define CPU_CFLAGS variable (overridden by cmdline value) that
+# overrides the one defined in arch.
+# - can define CPU_LDFLAGS variable (overridden by cmdline value) that
+# overrides the one defined in arch.
+# - can define CPU_ASFLAGS variable (overridden by cmdline value) that
+# overrides the one defined in arch.
+# - may override any previously defined variable
+#
+
+# ARCH =
+# CROSS =
+# MACHINE_CFLAGS =
+# MACHINE_LDFLAGS =
+# MACHINE_ASFLAGS =
+# CPU_CFLAGS =
+# CPU_LDFLAGS =
+# CPU_ASFLAGS =
+
+CPU_CFLAGS += -mfloat-abi=softfp
+
+MACHINE_CFLAGS += -march=armv7-a
+
+ifdef CONFIG_RTE_ARCH_ARM_TUNE
+MACHINE_CFLAGS += -mtune=$(CONFIG_RTE_ARCH_ARM_TUNE)
+endif
+
+ifeq ($(CONFIG_RTE_ARCH_ARM_NEON),y)
+MACHINE_CFLAGS += -mfpu=neon
+endif