From patchwork Mon Oct 26 16:37:33 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jan Viktorin X-Patchwork-Id: 8029 Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [IPv6:::1]) by dpdk.org (Postfix) with ESMTP id 9C8FA8E8C; Mon, 26 Oct 2015 17:39:44 +0100 (CET) Received: from wes1-so1.wedos.net (wes1-so1.wedos.net [46.28.106.15]) by dpdk.org (Postfix) with ESMTP id A7A678D8C for ; Mon, 26 Oct 2015 17:39:31 +0100 (CET) Received: from pcviktorin.fit.vutbr.cz (pcviktorin.fit.vutbr.cz [147.229.13.147]) by wes1-so1.wedos.net (Postfix) with ESMTPSA id 3nl21v2fbLz5GS; Mon, 26 Oct 2015 17:39:31 +0100 (CET) From: Jan Viktorin To: Thomas Monjalon , David Hunt , dev@dpdk.org Date: Mon, 26 Oct 2015 17:37:33 +0100 Message-Id: <1445877458-31052-12-git-send-email-viktorin@rehivetech.com> X-Mailer: git-send-email 2.6.1 In-Reply-To: <1445877458-31052-1-git-send-email-viktorin@rehivetech.com> References: <1445877458-31052-1-git-send-email-viktorin@rehivetech.com> Subject: [dpdk-dev] [PATCH v2 11/16] eal/arm: detect arm architecture in cpu flags X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Based on the patch by David Hunt and Armuta Zende: lib: added support for armv7 architecture Signed-off-by: Jan Viktorin Signed-off-by: Amruta Zende Signed-off-by: David Hunt --- lib/librte_eal/common/include/arch/arm/rte_cpuflags.h | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/lib/librte_eal/common/include/arch/arm/rte_cpuflags.h b/lib/librte_eal/common/include/arch/arm/rte_cpuflags.h index 1eadb33..17e13fc 100644 --- a/lib/librte_eal/common/include/arch/arm/rte_cpuflags.h +++ b/lib/librte_eal/common/include/arch/arm/rte_cpuflags.h @@ -52,10 +52,15 @@ extern "C" { #define AT_HWCAP2 26 #endif +#ifndef AT_PLATFORM +#define AT_PLATFORM 15 +#endif + /* software based registers */ enum cpu_register_t { REG_HWCAP = 0, REG_HWCAP2, + REG_PLATFORM, }; /** @@ -89,6 +94,8 @@ enum rte_cpu_flag_t { RTE_CPUFLAG_SHA1, RTE_CPUFLAG_SHA2, RTE_CPUFLAG_CRC32, + RTE_CPUFLAG_AARCH32, + RTE_CPUFLAG_AARCH64, /* The last item */ RTE_CPUFLAG_NUMFLAGS,/**< This should always be the last! */ }; @@ -121,6 +128,8 @@ static const struct feature_entry cpu_feature_table[] = { FEAT_DEF(SHA1, 0x00000001, 0, REG_HWCAP2, 2) FEAT_DEF(SHA2, 0x00000001, 0, REG_HWCAP2, 3) FEAT_DEF(CRC32, 0x00000001, 0, REG_HWCAP2, 4) + FEAT_DEF(AARCH32, 0x00000001, 0, REG_PLATFORM, 0) + FEAT_DEF(AARCH64, 0x00000001, 0, REG_PLATFORM, 1) }; /* @@ -141,6 +150,12 @@ rte_cpu_get_features(__attribute__((unused)) uint32_t leaf, out[REG_HWCAP] = auxv.a_un.a_val; else if (auxv.a_type == AT_HWCAP2) out[REG_HWCAP2] = auxv.a_un.a_val; + else if (auxv.a_type == AT_PLATFORM) { + if (!strcmp((const char *)auxv.a_un.a_val, "aarch32")) + out[REG_PLATFORM] = 0x0001; + else if (!strcmp((const char *)auxv.a_un.a_val, "aarch64")) + out[REG_PLATFORM] = 0x0002; + } } }