From patchwork Wed Oct 14 06:34:13 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wenzhuo Lu X-Patchwork-Id: 7574 Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [IPv6:::1]) by dpdk.org (Postfix) with ESMTP id 6774B9197; Wed, 14 Oct 2015 08:35:09 +0200 (CEST) Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by dpdk.org (Postfix) with ESMTP id 887A1918F for ; Wed, 14 Oct 2015 08:35:06 +0200 (CEST) Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga103.fm.intel.com with ESMTP; 13 Oct 2015 23:35:05 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.17,681,1437462000"; d="scan'208";a="792253464" Received: from shvmail01.sh.intel.com ([10.239.29.42]) by orsmga001.jf.intel.com with ESMTP; 13 Oct 2015 23:35:04 -0700 Received: from shecgisg004.sh.intel.com (shecgisg004.sh.intel.com [10.239.29.89]) by shvmail01.sh.intel.com with ESMTP id t9E6Z2vw032093; Wed, 14 Oct 2015 14:35:02 +0800 Received: from shecgisg004.sh.intel.com (localhost [127.0.0.1]) by shecgisg004.sh.intel.com (8.13.6/8.13.6/SuSE Linux 0.8) with ESMTP id t9E6Yxdu014931; Wed, 14 Oct 2015 14:35:01 +0800 Received: (from wenzhuol@localhost) by shecgisg004.sh.intel.com (8.13.6/8.13.6/Submit) id t9E6YxJi014927; Wed, 14 Oct 2015 14:34:59 +0800 From: Wenzhuo Lu To: dev@dpdk.org Date: Wed, 14 Oct 2015 14:34:13 +0800 Message-Id: <1444804479-14840-9-git-send-email-wenzhuo.lu@intel.com> X-Mailer: git-send-email 1.7.4.1 In-Reply-To: <1444804479-14840-1-git-send-email-wenzhuo.lu@intel.com> References: <1444804479-14840-1-git-send-email-wenzhuo.lu@intel.com> Subject: [dpdk-dev] [PATCH 08/34] e1000/base: remove E1000_WRITE_FLUSH for DH89XXCC_SGMII after commencing HW reset X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" For DH89XXCC_SGMII, write flush leaves registers of this device trashed (0xFFFFFFFF). Added check for this device. Also, after both for Port SW Reset and Device Reset case, platform should wait at least 3ms before reading any registers. Since waiting is conditionally executed only for Device Reset - removed the condition. Signed-off-by: Wenzhuo Lu --- drivers/net/e1000/base/e1000_82575.c | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/drivers/net/e1000/base/e1000_82575.c b/drivers/net/e1000/base/e1000_82575.c index 3dc8066..ab547ca 100644 --- a/drivers/net/e1000/base/e1000_82575.c +++ b/drivers/net/e1000/base/e1000_82575.c @@ -2490,11 +2490,17 @@ STATIC s32 e1000_reset_hw_82580(struct e1000_hw *hw) ctrl |= E1000_CTRL_RST; E1000_WRITE_REG(hw, E1000_CTRL, ctrl); - E1000_WRITE_FLUSH(hw); - /* Add delay to insure DEV_RST has time to complete */ - if (global_device_reset) - msec_delay(5); + switch (hw->device_id) { + case E1000_DEV_ID_DH89XXCC_SGMII: + break; + default: + E1000_WRITE_FLUSH(hw); + break; + } + + /* Add delay to insure DEV_RST or RST has time to complete */ + msec_delay(5); ret_val = e1000_get_auto_rd_done_generic(hw); if (ret_val) {