From patchwork Thu Oct 8 16:54:01 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rasesh Mody X-Patchwork-Id: 7486 Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [IPv6:::1]) by dpdk.org (Postfix) with ESMTP id 6BF688E68; Thu, 8 Oct 2015 18:54:55 +0200 (CEST) Received: from mx0a-0016ce01.pphosted.com (mx0a-0016ce01.pphosted.com [67.231.148.157]) by dpdk.org (Postfix) with ESMTP id 2E26D8E68 for ; Thu, 8 Oct 2015 18:54:54 +0200 (CEST) Received: from pps.filterd (m0045602.ppops.net [127.0.0.1]) by mx0a-0016ce01.pphosted.com (8.15.0.59/8.15.0.59) with SMTP id t98Gqbw8003038 for ; Thu, 8 Oct 2015 09:54:53 -0700 Received: from avcashub1.qlogic.com (avcashub1.qlogic.com [198.70.193.115]) by mx0a-0016ce01.pphosted.com with ESMTP id 1xdu9yg3hg-1 (version=TLSv1/SSLv3 cipher=AES128-SHA bits=128 verify=NOT) for ; Thu, 08 Oct 2015 09:54:53 -0700 Received: from avluser05.qlc.com (10.1.113.115) by qlc.com (10.1.4.190) with Microsoft SMTP Server id 14.3.235.1; Thu, 8 Oct 2015 09:54:52 -0700 Received: (from rmody@localhost) by avluser05.qlc.com (8.14.4/8.14.4/Submit) id t98Gsq5r002719; Thu, 8 Oct 2015 09:54:52 -0700 X-Authentication-Warning: avluser05.qlc.com: rmody set sender to rasesh.mody@qlogic.com using -f From: Rasesh Mody To: Date: Thu, 8 Oct 2015 09:54:01 -0700 Message-ID: <1444323245-2622-3-git-send-email-rasesh.mody@qlogic.com> X-Mailer: git-send-email 1.7.10.3 In-Reply-To: <1444323245-2622-1-git-send-email-rasesh.mody@qlogic.com> References: <1444323245-2622-1-git-send-email-rasesh.mody@qlogic.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=nai engine=5700 definitions=7947 signatures=670640 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 spamscore=0 clxscore=1015 suspectscore=3 malwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1507310000 definitions=main-1510080183 Cc: sony.chacko@qlogic.com Subject: [dpdk-dev] [PATCH 2/6] bnx2x: Linux 32bit enablement X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Compile tested. Signed-off-by: Rasesh Mody --- drivers/net/bnx2x/bnx2x.h | 12 ++++++------ drivers/net/bnx2x/bnx2x_ethdev.c | 2 +- drivers/net/bnx2x/bnx2x_rxtx.c | 11 +++++++---- drivers/net/bnx2x/bnx2x_vfpf.c | 4 ++-- drivers/net/bnx2x/debug.c | 32 ++++++++++++++++---------------- 5 files changed, 32 insertions(+), 29 deletions(-) diff --git a/drivers/net/bnx2x/bnx2x.h b/drivers/net/bnx2x/bnx2x.h index 724ae64..bfe4c43 100644 --- a/drivers/net/bnx2x/bnx2x.h +++ b/drivers/net/bnx2x/bnx2x.h @@ -1457,22 +1457,22 @@ void bnx2x_reg_write16(struct bnx2x_softc *sc, size_t offset, uint16_t val); void bnx2x_reg_write32(struct bnx2x_softc *sc, size_t offset, uint32_t val); #else #define bnx2x_reg_write8(sc, offset, val)\ - *((volatile uint8_t*)((uint64_t)sc->bar[BAR0].base_addr + offset)) = val + *((volatile uint8_t*)((uintptr_t)sc->bar[BAR0].base_addr + offset)) = val #define bnx2x_reg_write16(sc, offset, val)\ - *((volatile uint16_t*)((uint64_t)sc->bar[BAR0].base_addr + offset)) = val + *((volatile uint16_t*)((uintptr_t)sc->bar[BAR0].base_addr + offset)) = val #define bnx2x_reg_write32(sc, offset, val)\ - *((volatile uint32_t*)((uint64_t)sc->bar[BAR0].base_addr + offset)) = val + *((volatile uint32_t*)((uintptr_t)sc->bar[BAR0].base_addr + offset)) = val #define bnx2x_reg_read8(sc, offset)\ - (*((volatile uint8_t*)((uint64_t)sc->bar[BAR0].base_addr + offset))) + (*((volatile uint8_t*)((uintptr_t)sc->bar[BAR0].base_addr + offset))) #define bnx2x_reg_read16(sc, offset)\ - (*((volatile uint16_t*)((uint64_t)sc->bar[BAR0].base_addr + offset))) + (*((volatile uint16_t*)((uintptr_t)sc->bar[BAR0].base_addr + offset))) #define bnx2x_reg_read32(sc, offset)\ - (*((volatile uint32_t*)((uint64_t)sc->bar[BAR0].base_addr + offset))) + (*((volatile uint32_t*)((uintptr_t)sc->bar[BAR0].base_addr + offset))) #endif #define REG_ADDR(sc, offset) (((uint64_t)sc->bar[BAR0].base_addr) + (offset)) diff --git a/drivers/net/bnx2x/bnx2x_ethdev.c b/drivers/net/bnx2x/bnx2x_ethdev.c index a7608ef..5994791 100644 --- a/drivers/net/bnx2x/bnx2x_ethdev.c +++ b/drivers/net/bnx2x/bnx2x_ethdev.c @@ -439,7 +439,7 @@ bnx2x_common_dev_init(struct rte_eth_dev *eth_dev, int is_vf) sc->bar[BAR0].base_addr = (void *)pci_dev->mem_resource[0].addr; if (is_vf) sc->bar[BAR1].base_addr = (void *) - ((uint64_t)pci_dev->mem_resource[0].addr + PXP_VF_ADDR_DB_START); + ((uintptr_t)pci_dev->mem_resource[0].addr + PXP_VF_ADDR_DB_START); else sc->bar[BAR1].base_addr = pci_dev->mem_resource[2].addr; diff --git a/drivers/net/bnx2x/bnx2x_rxtx.c b/drivers/net/bnx2x/bnx2x_rxtx.c index c25a898..0f8b9bd 100644 --- a/drivers/net/bnx2x/bnx2x_rxtx.c +++ b/drivers/net/bnx2x/bnx2x_rxtx.c @@ -110,8 +110,10 @@ bnx2x_dev_rx_queue_setup(struct rte_eth_dev *dev, PMD_INIT_LOG(DEBUG, "fp[%02d] req_bd=%u, thresh=%u, usable_bd=%lu, " "total_bd=%lu, rx_pages=%u, cq_pages=%u", - queue_idx, nb_desc, rxq->rx_free_thresh, USABLE_RX_BD(rxq), - TOTAL_RX_BD(rxq), rxq->nb_rx_pages, rxq->nb_cq_pages); + queue_idx, nb_desc, rxq->rx_free_thresh, + (unsigned long)USABLE_RX_BD(rxq), + (unsigned long)TOTAL_RX_BD(rxq), rxq->nb_rx_pages, + rxq->nb_cq_pages); /* Allocate RX ring hardware descriptors */ dma_size = rxq->nb_rx_desc * sizeof(struct eth_rx_bd); @@ -291,8 +293,9 @@ bnx2x_dev_tx_queue_setup(struct rte_eth_dev *dev, PMD_INIT_LOG(DEBUG, "fp[%02d] req_bd=%u, thresh=%u, usable_bd=%lu, " "total_bd=%lu, tx_pages=%u", - queue_idx, nb_desc, txq->tx_free_thresh, USABLE_TX_BD(txq), - TOTAL_TX_BD(txq), txq->nb_tx_pages); + queue_idx, nb_desc, txq->tx_free_thresh, + (unsigned long)USABLE_TX_BD(txq), + (unsigned long)TOTAL_TX_BD(txq), txq->nb_tx_pages); /* Allocate TX ring hardware descriptors */ tsize = txq->nb_tx_desc * sizeof(union eth_tx_bd_types); diff --git a/drivers/net/bnx2x/bnx2x_vfpf.c b/drivers/net/bnx2x/bnx2x_vfpf.c index b3fcceb..765cc92 100644 --- a/drivers/net/bnx2x/bnx2x_vfpf.c +++ b/drivers/net/bnx2x/bnx2x_vfpf.c @@ -66,8 +66,8 @@ bnx2x_check_bull(struct bnx2x_softc *sc) /* add tlv to a buffer */ #define BNX2X_TLV_APPEND(_tlvs, _offset, _type, _length) \ - ((struct vf_first_tlv *)((uint64_t)_tlvs + _offset))->type = _type; \ - ((struct vf_first_tlv *)((uint64_t)_tlvs + _offset))->length = _length + ((struct vf_first_tlv *)((unsigned long)_tlvs + _offset))->type = _type; \ + ((struct vf_first_tlv *)((unsigned long)_tlvs + _offset))->length = _length /* Initiliaze header of the first tlv and clear mailbox*/ static void diff --git a/drivers/net/bnx2x/debug.c b/drivers/net/bnx2x/debug.c index ca59f55..656d9ca 100644 --- a/drivers/net/bnx2x/debug.c +++ b/drivers/net/bnx2x/debug.c @@ -23,8 +23,8 @@ void bnx2x_reg_write8(struct bnx2x_softc *sc, size_t offset, uint8_t val) { - PMD_REG_ACCESS_LOG(DEBUG, "offset=0x%08lx val=0x%02x", offset, val); - *((volatile uint8_t*)((uint64_t)sc->bar[BAR0].base_addr + offset)) = val; + PMD_REG_ACCESS_LOG(DEBUG, "offset=0x%08lx val=0x%02x", (unsigned long)offset, val); + *((volatile uint8_t*)((uintptr_t)sc->bar[BAR0].base_addr + offset)) = val; } void @@ -32,11 +32,11 @@ bnx2x_reg_write16(struct bnx2x_softc *sc, size_t offset, uint16_t val) { if ((offset % 2) != 0) { PMD_DRV_LOG(NOTICE, "Unaligned 16-bit write to 0x%08lx", - offset); + (unsigned long)offset); } - PMD_REG_ACCESS_LOG(DEBUG, "offset=0x%08lx val=0x%04x", offset, val); - *((volatile uint16_t*)((uint64_t)sc->bar[BAR0].base_addr + offset)) = val; + PMD_REG_ACCESS_LOG(DEBUG, "offset=0x%08lx val=0x%04x", (unsigned long)offset, val); + *((volatile uint16_t*)((uintptr_t)sc->bar[BAR0].base_addr + offset)) = val; } void @@ -44,11 +44,11 @@ bnx2x_reg_write32(struct bnx2x_softc *sc, size_t offset, uint32_t val) { if ((offset % 4) != 0) { PMD_DRV_LOG(NOTICE, "Unaligned 32-bit write to 0x%08lx", - offset); + (unsigned long)offset); } - PMD_REG_ACCESS_LOG(DEBUG, "offset=0x%08lx val=0x%08x", offset, val); - *((volatile uint32_t*)((uint64_t)sc->bar[BAR0].base_addr + offset)) = val; + PMD_REG_ACCESS_LOG(DEBUG, "offset=0x%08lx val=0x%08x", (unsigned long)offset, val); + *((volatile uint32_t*)((uintptr_t)sc->bar[BAR0].base_addr + offset)) = val; } uint8_t @@ -56,8 +56,8 @@ bnx2x_reg_read8(struct bnx2x_softc *sc, size_t offset) { uint8_t val; - val = (uint8_t)(*((volatile uint8_t*)((uint64_t)sc->bar[BAR0].base_addr + offset))); - PMD_REG_ACCESS_LOG(DEBUG, "offset=0x%08lx val=0x%02x", offset, val); + val = (uint8_t)(*((volatile uint8_t*)((uintptr_t)sc->bar[BAR0].base_addr + offset))); + PMD_REG_ACCESS_LOG(DEBUG, "offset=0x%08lx val=0x%02x", (unsigned long)offset, val); return (val); } @@ -69,11 +69,11 @@ bnx2x_reg_read16(struct bnx2x_softc *sc, size_t offset) if ((offset % 2) != 0) { PMD_DRV_LOG(NOTICE, "Unaligned 16-bit read from 0x%08lx", - offset); + (unsigned long)offset); } - val = (uint16_t)(*((volatile uint16_t*)((uint64_t)sc->bar[BAR0].base_addr + offset))); - PMD_REG_ACCESS_LOG(DEBUG, "offset=0x%08lx val=0x%08x", offset, val); + val = (uint16_t)(*((volatile uint16_t*)((uintptr_t)sc->bar[BAR0].base_addr + offset))); + PMD_REG_ACCESS_LOG(DEBUG, "offset=0x%08lx val=0x%08x", (unsigned long)offset, val); return (val); } @@ -85,12 +85,12 @@ bnx2x_reg_read32(struct bnx2x_softc *sc, size_t offset) if ((offset % 4) != 0) { PMD_DRV_LOG(NOTICE, "Unaligned 32-bit read from 0x%08lx", - offset); + (unsigned long)offset); return 0; } - val = (uint32_t)(*((volatile uint32_t*)((uint64_t)sc->bar[BAR0].base_addr + offset))); - PMD_REG_ACCESS_LOG(DEBUG, "offset=0x%08lx val=0x%08x", offset, val); + val = (uint32_t)(*((volatile uint32_t*)((uintptr_t)sc->bar[BAR0].base_addr + offset))); + PMD_REG_ACCESS_LOG(DEBUG, "offset=0x%08lx val=0x%08x", (unsigned long)offset, val); return (val); }