diff mbox

[dpdk-dev] ixgbe: prefetch cacheline after pointer becomes valid

Message ID 1443140606-18241-1-git-send-email-zoltan.kiss@linaro.org (mailing list archive)
State Superseded, archived
Headers

Commit Message

Zoltan Kiss Sept. 25, 2015, 12:23 a.m. UTC 
  At the original point the rx_pkts[pos( + n)] pointers are not initialized, so
the code is prefetching random data.

Signed-off-by: Zoltan Kiss <zoltan.kiss@linaro.org>

Comments

John McNamara Sept. 25, 2015, 11:47 a.m. UTC | #1 
> -----Original Message-----
> From: dev [mailto:dev-bounces@dpdk.org] On Behalf Of Zoltan Kiss
> Sent: Friday, September 25, 2015 1:23 AM
> To: dev@dpdk.org
> Subject: [dpdk-dev] [PATCH] ixgbe: prefetch cacheline after pointer
> becomes valid
> 
> +               if (split_packet) {
> +                       rte_prefetch0(&rx_pkts[pos]->cacheline1);
> +                       rte_prefetch0(&rx_pkts[pos + 1]->cacheline1);
> +                       rte_prefetch0(&rx_pkts[pos + 2]->cacheline1);
> +                       rte_prefetch0(&rx_pkts[pos + 3]->cacheline1);
> +               }
> +
>                 /* A* mask out 0~3 bits RSS type */
>                 descs[3] = _mm_and_si128(descs0[3], desc_mask);
>                 descs[2] = _mm_and_si128(descs0[2], desc_mask);

Hi,

This patch doesn't apply cleanly. It looks like all the tabs have been replaced with spaces.

John.
Bruce Richardson Sept. 25, 2015, 3:22 p.m. UTC | #2 
On Thu, Sep 24, 2015 at 05:23:26PM -0700, Zoltan Kiss wrote:
> At the original point the rx_pkts[pos( + n)] pointers are not initialized, so
> the code is prefetching random data.
> 
> Signed-off-by: Zoltan Kiss <zoltan.kiss@linaro.org>
> 

Apart from the whitespace issues pointed out by John, this fix looks ok and
testing shows no performance impact (as expected).

/Bruce
Zoltan Kiss Sept. 25, 2015, 5:42 p.m. UTC | #3 
On 25/09/15 04:47, Mcnamara, John wrote:
>> -----Original Message-----
>> From: dev [mailto:dev-bounces@dpdk.org] On Behalf Of Zoltan Kiss
>> Sent: Friday, September 25, 2015 1:23 AM
>> To: dev@dpdk.org
>> Subject: [dpdk-dev] [PATCH] ixgbe: prefetch cacheline after pointer
>> becomes valid
>>
>> +               if (split_packet) {
>> +                       rte_prefetch0(&rx_pkts[pos]->cacheline1);
>> +                       rte_prefetch0(&rx_pkts[pos + 1]->cacheline1);
>> +                       rte_prefetch0(&rx_pkts[pos + 2]->cacheline1);
>> +                       rte_prefetch0(&rx_pkts[pos + 3]->cacheline1);
>> +               }
>> +
>>                  /* A* mask out 0~3 bits RSS type */
>>                  descs[3] = _mm_and_si128(descs0[3], desc_mask);
>>                  descs[2] = _mm_and_si128(descs0[2], desc_mask);
> Hi,
>
> This patch doesn't apply cleanly. It looks like all the tabs have been replaced with spaces.

Sorry, my bad, I'll resend
>
> John.
>
>
diff mbox

Patch

diff --git a/drivers/net/ixgbe/ixgbe_rxtx_vec.c b/drivers/net/ixgbe/ixgbe_rxtx_vec.c
index 3c6d8c5..ccd93c7 100644
--- a/drivers/net/ixgbe/ixgbe_rxtx_vec.c
+++ b/drivers/net/ixgbe/ixgbe_rxtx_vec.c
@@ -284,13 +284,6 @@  _recv_raw_pkts_vec(struct ixgbe_rx_queue *rxq, struct rte_mbuf **rx_pkts,
                __m128i zero, staterr, sterr_tmp1, sterr_tmp2;
                __m128i mbp1, mbp2; /* two mbuf pointer in one XMM reg. */
 
-               if (split_packet) {
-                       rte_prefetch0(&rx_pkts[pos]->cacheline1);
-                       rte_prefetch0(&rx_pkts[pos + 1]->cacheline1);
-                       rte_prefetch0(&rx_pkts[pos + 2]->cacheline1);
-                       rte_prefetch0(&rx_pkts[pos + 3]->cacheline1);
-               }
-
                /* B.1 load 1 mbuf point */
                mbp1 = _mm_loadu_si128((__m128i *)&sw_ring[pos]);
 
@@ -312,6 +305,13 @@  _recv_raw_pkts_vec(struct ixgbe_rx_queue *rxq, struct rte_mbuf **rx_pkts,
                /* B.2 copy 2 mbuf point into rx_pkts  */
                _mm_storeu_si128((__m128i *)&rx_pkts[pos+2], mbp2);
 
+               if (split_packet) {
+                       rte_prefetch0(&rx_pkts[pos]->cacheline1);
+                       rte_prefetch0(&rx_pkts[pos + 1]->cacheline1);
+                       rte_prefetch0(&rx_pkts[pos + 2]->cacheline1);
+                       rte_prefetch0(&rx_pkts[pos + 3]->cacheline1);
+               }
+
                /* A* mask out 0~3 bits RSS type */
                descs[3] = _mm_and_si128(descs0[3], desc_mask);
                descs[2] = _mm_and_si128(descs0[2], desc_mask);