From patchwork Sun Sep 6 07:11:54 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jingjing Wu X-Patchwork-Id: 6938 Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [IPv6:::1]) by dpdk.org (Postfix) with ESMTP id 1491793A0; Sun, 6 Sep 2015 09:13:46 +0200 (CEST) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by dpdk.org (Postfix) with ESMTP id 47EE693A0 for ; Sun, 6 Sep 2015 09:13:44 +0200 (CEST) Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga103.jf.intel.com with ESMTP; 06 Sep 2015 00:13:43 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.17,478,1437462000"; d="scan'208";a="763416094" Received: from shvmail01.sh.intel.com ([10.239.29.42]) by orsmga001.jf.intel.com with ESMTP; 06 Sep 2015 00:13:42 -0700 Received: from shecgisg004.sh.intel.com (shecgisg004.sh.intel.com [10.239.29.89]) by shvmail01.sh.intel.com with ESMTP id t867Den4019775; Sun, 6 Sep 2015 15:13:40 +0800 Received: from shecgisg004.sh.intel.com (localhost [127.0.0.1]) by shecgisg004.sh.intel.com (8.13.6/8.13.6/SuSE Linux 0.8) with ESMTP id t867Dcjp026519; Sun, 6 Sep 2015 15:13:40 +0800 Received: (from wujingji@localhost) by shecgisg004.sh.intel.com (8.13.6/8.13.6/Submit) id t867DcYF026515; Sun, 6 Sep 2015 15:13:38 +0800 From: Jingjing Wu To: dev@dpdk.org Date: Sun, 6 Sep 2015 15:11:54 +0800 Message-Id: <1441523526-26202-41-git-send-email-jingjing.wu@intel.com> X-Mailer: git-send-email 1.7.4.1 In-Reply-To: <1441523526-26202-1-git-send-email-jingjing.wu@intel.com> References: <1441523526-26202-1-git-send-email-jingjing.wu@intel.com> Subject: [dpdk-dev] [PATCH 40/52] i40e/base: add WR_CSR_PROT wol/proxy capability parsing X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Adds support to retrieve and parse WoL/Proxy capabilities from the device/function list. Also saves WR_CSR_PROT field from DEV/FUNC capabilities. Signed-off-by: Jingjing Wu --- drivers/net/i40e/base/i40e_common.c | 29 +++++++++++++++++++++++++---- drivers/net/i40e/base/i40e_type.h | 23 +++++++++++++++++++++++ 2 files changed, 48 insertions(+), 4 deletions(-) diff --git a/drivers/net/i40e/base/i40e_common.c b/drivers/net/i40e/base/i40e_common.c index fe86096..320428f 100644 --- a/drivers/net/i40e/base/i40e_common.c +++ b/drivers/net/i40e/base/i40e_common.c @@ -3330,6 +3330,9 @@ i40e_aq_erase_nvm_exit: #define I40E_DEV_FUNC_CAP_NPAR 0x03 #define I40E_DEV_FUNC_CAP_OS2BMC 0x04 #define I40E_DEV_FUNC_CAP_VALID_FUNC 0x05 +#ifdef X722_SUPPORT +#define I40E_DEV_FUNC_CAP_WOL_PROXY 0x08 +#endif #define I40E_DEV_FUNC_CAP_SRIOV_1_1 0x12 #define I40E_DEV_FUNC_CAP_VF 0x13 #define I40E_DEV_FUNC_CAP_VMDQ 0x14 @@ -3352,6 +3355,7 @@ i40e_aq_erase_nvm_exit: #define I40E_DEV_FUNC_CAP_LED 0x61 #define I40E_DEV_FUNC_CAP_SDP 0x62 #define I40E_DEV_FUNC_CAP_MDIO 0x63 +#define I40E_DEV_FUNC_CAP_WR_CSR_PROT 0x64 /** * i40e_parse_discover_capabilities @@ -3510,6 +3514,23 @@ STATIC void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff, p->fd_filters_guaranteed = number; p->fd_filters_best_effort = logical_id; break; + case I40E_DEV_FUNC_CAP_WR_CSR_PROT: + p->wr_csr_prot = (u64)number; + p->wr_csr_prot |= (u64)logical_id << 32; + break; +#ifdef X722_SUPPORT + case I40E_DEV_FUNC_CAP_WOL_PROXY: + hw->num_wol_proxy_filters = (u16)number; + hw->wol_proxy_vsi_seid = (u16)logical_id; + p->apm_wol_support = phys_id & I40E_WOL_SUPPORT_MASK; + if (phys_id & I40E_ACPI_PROGRAMMING_METHOD_MASK) + p->acpi_prog_method = I40E_ACPI_PROGRAMMING_METHOD_AQC_FPK; + else + p->acpi_prog_method = I40E_ACPI_PROGRAMMING_METHOD_HW_FVL; + p->proxy_support = (phys_id & I40E_PROXY_SUPPORT_MASK) ? 1 : 0; + p->proxy_support = p->proxy_support; + break; +#endif default: break; } @@ -5609,11 +5630,11 @@ enum i40e_status_code i40e_read_bw_from_alt_ram(struct i40e_hw *hw, /* Calculate the address of the min/max bw registers */ max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET + - I40E_ALT_STRUCT_MAX_BW_OFFSET + - (I40E_ALT_STRUCT_DWORDS_PER_PF*hw->pf_id); + I40E_ALT_STRUCT_MAX_BW_OFFSET + + (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id); min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET + - I40E_ALT_STRUCT_MIN_BW_OFFSET + - (I40E_ALT_STRUCT_DWORDS_PER_PF*hw->pf_id); + I40E_ALT_STRUCT_MIN_BW_OFFSET + + (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id); /* Read the bandwidths from alt ram */ status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw, diff --git a/drivers/net/i40e/base/i40e_type.h b/drivers/net/i40e/base/i40e_type.h index b5b5890..39d8a89 100644 --- a/drivers/net/i40e/base/i40e_type.h +++ b/drivers/net/i40e/base/i40e_type.h @@ -314,6 +314,17 @@ struct i40e_phy_info { #define I40E_HW_CAP_MDIO_PORT_MODE_MDIO 0 #define I40E_HW_CAP_MDIO_PORT_MODE_I2C 1 +#ifdef X722_SUPPORT +enum i40e_acpi_programming_method { + I40E_ACPI_PROGRAMMING_METHOD_HW_FVL = 0, + I40E_ACPI_PROGRAMMING_METHOD_AQC_FPK = 1 +}; + +#define I40E_WOL_SUPPORT_MASK 1 +#define I40E_ACPI_PROGRAMMING_METHOD_MASK (1 << 1) +#define I40E_PROXY_SUPPORT_MASK (1 << 2) + +#endif /* Capabilities of a PF or a VF or the whole device */ struct i40e_hw_capabilities { u32 switch_mode; @@ -371,6 +382,12 @@ struct i40e_hw_capabilities { u8 rx_buf_chain_len; u32 enabled_tcmap; u32 maxtc; + u64 wr_csr_prot; +#ifdef X722_SUPPORT + bool apm_wol_support; + enum i40e_acpi_programming_method acpi_prog_method; + bool proxy_support; +#endif }; struct i40e_mac_info { @@ -628,6 +645,12 @@ struct i40e_hw { struct i40e_dcbx_config remote_dcbx_config; /* Peer Cfg */ struct i40e_dcbx_config desired_dcbx_config; /* CEE Desired Cfg */ +#ifdef X722_SUPPORT + /* WoL and proxy support */ + u16 num_wol_proxy_filters; + u16 wol_proxy_vsi_seid; + +#endif /* debug mask */ u32 debug_mask; #ifndef I40E_NDIS_SUPPORT