From patchwork Fri Jul 31 01:20:30 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wenzhuo Lu X-Patchwork-Id: 6674 Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [IPv6:::1]) by dpdk.org (Postfix) with ESMTP id 3B1C5C6BA; Fri, 31 Jul 2015 03:20:40 +0200 (CEST) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by dpdk.org (Postfix) with ESMTP id 2D601C6A0 for ; Fri, 31 Jul 2015 03:20:39 +0200 (CEST) Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga102.jf.intel.com with ESMTP; 30 Jul 2015 18:20:39 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.15,580,1432623600"; d="scan'208";a="616453750" Received: from shvmail01.sh.intel.com ([10.239.29.42]) by orsmga003.jf.intel.com with ESMTP; 30 Jul 2015 18:20:37 -0700 Received: from shecgisg004.sh.intel.com (shecgisg004.sh.intel.com [10.239.29.89]) by shvmail01.sh.intel.com with ESMTP id t6V1KYHi010729; Fri, 31 Jul 2015 09:20:34 +0800 Received: from shecgisg004.sh.intel.com (localhost [127.0.0.1]) by shecgisg004.sh.intel.com (8.13.6/8.13.6/SuSE Linux 0.8) with ESMTP id t6V1KWcA025310; Fri, 31 Jul 2015 09:20:34 +0800 Received: (from wenzhuol@localhost) by shecgisg004.sh.intel.com (8.13.6/8.13.6/Submit) id t6V1KV1a025306; Fri, 31 Jul 2015 09:20:31 +0800 From: Wenzhuo Lu To: dev@dpdk.org Date: Fri, 31 Jul 2015 09:20:30 +0800 Message-Id: <1438305630-25275-1-git-send-email-wenzhuo.lu@intel.com> X-Mailer: git-send-email 1.7.4.1 In-Reply-To: <1438245257-7328-1-git-send-email-wenzhuo.lu@intel.com> References: <1438245257-7328-1-git-send-email-wenzhuo.lu@intel.com> Subject: [dpdk-dev] [PATCH v2] e1000: fix ieee1588 timestamp issue X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Ieee1588 reads system time to set its timestamp. On 1G NICs, for example, i350, system time is disabled by default. It means the ieee1588 timestamp will always be 0. This patch enables system time when ieee1588 is enabled. v2 changes: * move the macro to the top of the file with the other timesync defines. Signed-off-by: Wenzhuo Lu Acked-by: John McNamara --- drivers/net/e1000/igb_ethdev.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/net/e1000/igb_ethdev.c b/drivers/net/e1000/igb_ethdev.c index 56734a3..b2f57c4 100644 --- a/drivers/net/e1000/igb_ethdev.c +++ b/drivers/net/e1000/igb_ethdev.c @@ -82,6 +82,7 @@ #define E1000_TIMINCA_INCVALUE 16000000 #define E1000_TIMINCA_INIT ((0x02 << E1000_TIMINCA_16NS_SHIFT) \ | E1000_TIMINCA_INCVALUE) +#define E1000_TSAUXC_DISABLE_SYSTIME 0x80000000 static int eth_igb_configure(struct rte_eth_dev *dev); static int eth_igb_start(struct rte_eth_dev *dev); @@ -3903,6 +3904,12 @@ igb_timesync_enable(struct rte_eth_dev *dev) { struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); uint32_t tsync_ctl; + uint32_t tsauxc; + + /* Enable system time for it isn't on by default. */ + tsauxc = E1000_READ_REG(hw, E1000_TSAUXC); + tsauxc &= ~E1000_TSAUXC_DISABLE_SYSTIME; + E1000_WRITE_REG(hw, E1000_TSAUXC, tsauxc); /* Start incrementing the register used to timestamp PTP packets. */ E1000_WRITE_REG(hw, E1000_TIMINCA, E1000_TIMINCA_INIT);