From patchwork Thu Jul 16 06:45:34 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: xuelin.shi@freescale.com X-Patchwork-Id: 6449 Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [IPv6:::1]) by dpdk.org (Postfix) with ESMTP id 600065A7A; Thu, 16 Jul 2015 09:44:54 +0200 (CEST) Received: from na01-bn1-obe.outbound.protection.outlook.com (mail-bn1on0138.outbound.protection.outlook.com [157.56.110.138]) by dpdk.org (Postfix) with ESMTP id C0D16376D for ; Thu, 16 Jul 2015 09:44:51 +0200 (CEST) Received: from BN3PR0301CA0001.namprd03.prod.outlook.com (10.160.180.139) by BY1PR03MB1338.namprd03.prod.outlook.com (10.162.109.20) with Microsoft SMTP Server (TLS) id 15.1.213.14; Thu, 16 Jul 2015 07:44:49 +0000 Received: from BN1BFFO11FD038.protection.gbl (2a01:111:f400:7c10::1:163) by BN3PR0301CA0001.outlook.office365.com (2a01:111:e400:4000::11) with Microsoft SMTP Server (TLS) id 15.1.219.17 via Frontend Transport; Thu, 16 Jul 2015 07:44:49 +0000 Authentication-Results: spf=fail (sender IP is 192.88.168.50) smtp.mailfrom=freescale.com; freescale.mail.onmicrosoft.com; dkim=none (message not signed) header.d=none; Received-SPF: Fail (protection.outlook.com: domain of freescale.com does not designate 192.88.168.50 as permitted sender) receiver=protection.outlook.com; client-ip=192.88.168.50; helo=tx30smr01.am.freescale.net; Received: from tx30smr01.am.freescale.net (192.88.168.50) by BN1BFFO11FD038.mail.protection.outlook.com (10.58.144.101) with Microsoft SMTP Server (TLS) id 15.1.213.8 via Frontend Transport; Thu, 16 Jul 2015 07:44:49 +0000 Received: from localhost (rock.ap.freescale.net [10.193.20.106]) by tx30smr01.am.freescale.net (8.14.3/8.14.0) with ESMTP id t6G7iiZR012111; Thu, 16 Jul 2015 00:44:45 -0700 From: To: Date: Thu, 16 Jul 2015 14:45:34 +0800 Message-ID: <1437029134-25191-1-git-send-email-xuelin.shi@freescale.com> X-Mailer: git-send-email 1.8.4 X-EOPAttributedMessage: 0 X-Microsoft-Exchange-Diagnostics: 1; BN1BFFO11FD038; 1:lCXsksm9lMvPHDMGtKzyI+Vr1iIif/U+BM53wfRv3wzK67WAOdenqeAb7rZfr4FvLQvPgSg3xOq8MS83C/z/itSn3lsipSWEXKBQ0sdnhfVjzwYJBHRfLFbZwGAkq8yHfdnNHqzZo8V8JXZAB+9TT51gCKeNh1D5fMdwOLoRBxmC9O1bTbKpC0hL1gLc5lxaFPsaTZK1zjn/I1L6QMjnQjjkQIpsj0NWQKdOyIGLLZaB+IBtusXnAEgmIberpLPGJp9cIrBU8zh29ojKenIoVj6C01pY+O8FVEj3JHxl4zew5aYPDggpWMo2WbM0wARcnCGHkMdM1O1P6LFfM8TlqMtdZ2AgFHCkIvpt/w94gdwv0BdgkuQyrx7TLf4u7SW27yd12F6ECzjlmuAMxV7qJOJbuXvYZFIUyNiZ4KR1q6MuOxGbLpFCFH0pbBCyYhb5 X-Forefront-Antispam-Report: CIP:192.88.168.50; CTRY:US; IPV:NLI; EFV:NLI; SFV:NSPM; SFS:(10019020)(6009001)(2980300002)(339900001)(189002)(199003)(19580405001)(77156002)(86152002)(77096005)(106466001)(105606002)(86362001)(50466002)(189998001)(57986006)(48376002)(85426001)(92566002)(47776003)(76506005)(19580395003)(50986999)(36756003)(5003940100001)(229853001)(107886002)(2351001)(5001960100002)(46102003)(5001920100001)(62966003)(6806004)(104016003)(87936001)(33646002)(50226001)(110136002)(4001430100001); DIR:OUT; SFP:1102; SCL:1; SRVR:BY1PR03MB1338; H:tx30smr01.am.freescale.net; FPR:; SPF:Fail; MLV:sfv; MX:1; A:1; LANG:en; MIME-Version: 1.0 X-Microsoft-Exchange-Diagnostics: 1; BY1PR03MB1338; 2:1CH6qm232JgtyOODuXwYy/PG0QDCc0SptOEXLebSD4rZJStHGCLrzLV3s5hb8s+D; 3:WdKb81CWpsrn6e4kOqVnyIiYZ51mbs+WkV5CsSEK15Wxuaf4UA8OSvC/nUJct76FdDAxuW9rsria5lYS9HSzfwpDtko2xYxfLUUFpTWLZ1Pm8PC5YC/i4RDZUK2zncsOS0cktZhGqFlJStOzGaUoBAw/16g8LFwh4NzUmkZJA9lixwbwc9aOfPf3V3bkj1AUPpW0+0+zRoEDANwT4NrmayGsDCUcPJU9ihaC9GtYi9Q=; 25:d7xEa/2rzIpyNMj1ut+PBzZvTS4nT7c8j27NedY25Tb9UNh0cWWpT5h72T9bTnh8x/n2ycfq5/KkZXR3FcJqEwDsPC/mU7L6S/gp64ZNkNT4RmsW5K5Hiw+KmLWqNiUSr54m9vOVjezGX2IgfGf0PRP5Ja8zasIc+apy4B1H9fpyaq4KE2OcJeFUPytt3TBtdsd/CWPCE7Csm3ZnZ4vA9MwoyBHLK7zPU6z0WSqv0WCJ2INzezGu+ml4sd+aFVb7; 20:gQ7xMqdNpN/N+8dGGSr6cxaFANUphSwtkzFxNRWN/EK7Ppy65yec+S+dHi+1d3hdvPu+eFuajv2Hy7TaWdROqg5yU4TNzQPJxI7OR0gr0wdjVGayMvDkzSwj8IjHXS46bXkJgYyTf4egw4g2Sri28r5qQBneO2967LsrpjDIA1/ZoHcZYzOi7HIFuPaJvUdruNmXIWHhDjC37JzhywK5h2yZ1Roo1fksaQEMzbyRZs+RbnS7G84YZ+vfMRFmmj8yVBXalDjQST6YBOfcdWr3ZTGAM4mVcnxO9Yk6VaozjJ4gVLrCDeFV3aFfJqHFVbKWBSlhFCkNvQq/7Fh6ysc18eOEOMSz/Vb/bckP9bCglFM= X-Microsoft-Antispam: UriScan:;BCL:0;PCL:0;RULEID:;SRVR:BY1PR03MB1338; BY1PR03MB1338: X-MS-Exchange-Organization-RulesExecuted X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-Test: UriScan:; X-Exchange-Antispam-Report-CFA-Test: BCL:0; PCL:0; RULEID:(601004)(5005006)(3002001); SRVR:BY1PR03MB1338; BCL:0; PCL:0; RULEID:; SRVR:BY1PR03MB1338; X-Microsoft-Exchange-Diagnostics: 1; BY1PR03MB1338; 4:CknsHeMAA+9MqewGaUELJhBscbSsCfVpD6XwuULhlv0Eixvy6637U4aijJS0JFTcWhcM9wkcFdDr+w1mOAe+2Dh0ZpixD+5AXrL8MTYCl4YYynaICBywsEgetl4K2hu83vm3eWaUM+JoAxitV7Tx0Dg2hPc3U8nh4rDnkyWl1KygZIBi0gPExsQubv4dMgNGVoBqfU6+GwS1KkLhOM6WLYZIDWAPtszUAcJdOhRVH1YiX7n+f6+Qq1kpckpWBk+aVx1i2YeZmeMpPfSlwmxY3FRDUWwDYdRJu5G7vtfivkg= X-Forefront-PRVS: 0639027A9E X-Microsoft-Exchange-Diagnostics: =?us-ascii?Q?1; BY1PR03MB1338; 23:p67v7H1kSH2inwQHWLL1Vn8G6338s0npBc8W9QxSo?= =?us-ascii?Q?w9Cy6+IVvdll9eCpW9aDWuNpQPue4DyaJP3EbwrWVTC1D8ciRBOJ7vKe4SFf?= =?us-ascii?Q?5lNnWBxgUYFEWawRJ5CVZB+FRxSiXZRZggeFfs8r7WoFJVSjvfxNdSmSRbyL?= =?us-ascii?Q?AMoF8F4P4ZqK3OoJKBykAM4UH+8oCdV+SapVq8FapT41JGCbwMj2A5kcffGM?= =?us-ascii?Q?drjsh9LPYCBGoiH0bs5xom1zz/X87JMO6EhEExN2+DaLHq7NLdkT47AldIOu?= =?us-ascii?Q?r+nn1XZs1KuLj7d5Vfrbme0GX8oCJzb07Jf2h+zyERMHMywjwvegbBPjoRKF?= =?us-ascii?Q?zwEtT85LOgCxPHz6PSBLDW4N0WV2oDGvkEL9nNHxiegZJAnuqyMmTw51vWtr?= =?us-ascii?Q?axQbUR+lc1k7evc8KJjZ/0akbCnJ8/p/vWlOr96Lf4KkkDDqN23dptxaSndW?= =?us-ascii?Q?bERLk7Ku745rDJ/4jzwdgLMxniUZMVHY7ww0fjwKF3DxXAKBKzizyZPVnzqH?= =?us-ascii?Q?AvOQGdovXB36Jpt5ndprzl1OY9Olv1oyVG1VKp8I7xEKoKBfglYFkP9wFLQQ?= =?us-ascii?Q?iqTEt0Mb9DoNAqtOjlkpCNGJW7qJoW9QZzgNv3fPalHZFne1TxDi4KqoqEu7?= =?us-ascii?Q?EW4XHMZWKEklg8TgHtvmdpr1gAM3H+BhpvdXQu6pMjoXuFVnDX3Y9Hb1gJb6?= =?us-ascii?Q?nsDeGeKECt5x/p7sKf/OmbW6miCvRS0DsaanI6eWoJYAPHJ7LkeTGyG4qthe?= =?us-ascii?Q?h5wBY1wOrXv4qgQyxapHt10R3dBgDdwSHAwOH+TjFzKv9LPCn3bs+EzvqGrv?= =?us-ascii?Q?6j346ADIB1wwhYOwLNL3ZYOZvSaeEmSBnIp3lfvE/vMrQbS44ljWTY04PXOc?= =?us-ascii?Q?qjbc9J9XbfgHAO0hJN5uUI0OqxPgNg2szBBHzlFX9wsYYUkYSfKcg/Ygnlff?= =?us-ascii?Q?6hz5qPzyT+lH/IKfOYBAcfvFqBC9qtN6p05VrOxsJPOPeql5Vt/HwQAYgwEl?= =?us-ascii?Q?4wQLcox7YgALJFZ9hkyEWsM?= X-Microsoft-Exchange-Diagnostics: 1; BY1PR03MB1338; 5:Jty9IzbiDbJxlbIIVxKiBh/6rHVbew4W/9ft06LmsSfi+Pg4lYbaAyXOa+T/3HpowbZTERAB4uGc5J9zFPyOeGPdLZrSPw4fskc/VPDdLohCLSJqpGO2OBjRz6T4pd6M5da14sQT5hGWjXDQTvns0g==; 24:6r2kBzOQjdkDPShCcWUI9afkGTgoQN3fiAFGiCufjCO+sMy5O7k+ElTykh9VDH02SVswwZiU8J99TgoPmmebxBWYwme0r3MKT8nH3fVlIhY=; 20:ZcWiG+95W5Vwk3UNM6AOCIw5acWkaHqbmcuF7YYtJr52MwXF+S4uGxG6eeOjlxUY6ZVrzf1P+iKXkQ5kXF1c8g== X-OriginatorOrg: freescale.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Jul 2015 07:44:49.2678 (UTC) X-MS-Exchange-CrossTenant-Id: 710a03f5-10f6-4d38-9ff4-a80b81da590d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=710a03f5-10f6-4d38-9ff4-a80b81da590d; Ip=[192.88.168.50]; Helo=[tx30smr01.am.freescale.net] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY1PR03MB1338 Cc: dev@dpdk.org, Xuelin Shi Subject: [dpdk-dev] [PATCH v4] enforce rules of the cpu and ixgbe exchange data. X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Xuelin Shi 1. cpu use data owned by ixgbe must use rte_le_to_cpu_xx(...) 2. cpu fill data to ixgbe must use rte_cpu_to_le_xx(...) 3. checking pci status with converted constant. Signed-off-by: Xuelin Shi --- drivers/net/ixgbe/ixgbe_rxtx.c | 77 ++++++++++++++++++++++++++++-------------- 1 file changed, 51 insertions(+), 26 deletions(-) diff --git a/drivers/net/ixgbe/ixgbe_rxtx.c b/drivers/net/ixgbe/ixgbe_rxtx.c index a7c94a9..5a6cc1c 100644 --- a/drivers/net/ixgbe/ixgbe_rxtx.c +++ b/drivers/net/ixgbe/ixgbe_rxtx.c @@ -130,7 +130,7 @@ ixgbe_tx_free_bufs(struct ixgbe_tx_queue *txq) /* check DD bit on threshold descriptor */ status = txq->tx_ring[txq->tx_next_dd].wb.status; - if (! (status & IXGBE_ADVTXD_STAT_DD)) + if (!(status & rte_cpu_to_le_32(IXGBE_ADVTXD_STAT_DD))) return 0; /* @@ -175,11 +175,14 @@ tx4(volatile union ixgbe_adv_tx_desc *txdp, struct rte_mbuf **pkts) pkt_len = (*pkts)->data_len; /* write data to descriptor */ - txdp->read.buffer_addr = buf_dma_addr; + txdp->read.buffer_addr = rte_cpu_to_le_64(buf_dma_addr); + txdp->read.cmd_type_len = - ((uint32_t)DCMD_DTYP_FLAGS | pkt_len); + rte_cpu_to_le_32((uint32_t)DCMD_DTYP_FLAGS | pkt_len); + txdp->read.olinfo_status = - (pkt_len << IXGBE_ADVTXD_PAYLEN_SHIFT); + rte_cpu_to_le_32(pkt_len << IXGBE_ADVTXD_PAYLEN_SHIFT); + rte_prefetch0(&(*pkts)->pool); } } @@ -195,11 +198,14 @@ tx1(volatile union ixgbe_adv_tx_desc *txdp, struct rte_mbuf **pkts) pkt_len = (*pkts)->data_len; /* write data to descriptor */ - txdp->read.buffer_addr = buf_dma_addr; + txdp->read.buffer_addr = rte_cpu_to_le_64(buf_dma_addr); + txdp->read.cmd_type_len = - ((uint32_t)DCMD_DTYP_FLAGS | pkt_len); + rte_cpu_to_le_32((uint32_t)DCMD_DTYP_FLAGS | pkt_len); + txdp->read.olinfo_status = - (pkt_len << IXGBE_ADVTXD_PAYLEN_SHIFT); + rte_cpu_to_le_32(pkt_len << IXGBE_ADVTXD_PAYLEN_SHIFT); + rte_prefetch0(&(*pkts)->pool); } @@ -511,6 +517,7 @@ ixgbe_xmit_cleanup(struct ixgbe_tx_queue *txq) uint16_t nb_tx_desc = txq->nb_tx_desc; uint16_t desc_to_clean_to; uint16_t nb_tx_to_clean; + uint32_t stat; /* Determine the last descriptor needing to be cleaned */ desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->tx_rs_thresh); @@ -519,7 +526,9 @@ ixgbe_xmit_cleanup(struct ixgbe_tx_queue *txq) /* Check to make sure the last descriptor to clean is done */ desc_to_clean_to = sw_ring[desc_to_clean_to].last_id; - if (! (txr[desc_to_clean_to].wb.status & IXGBE_TXD_STAT_DD)) + + stat = txr[desc_to_clean_to].wb.status; + if (!(stat & rte_cpu_to_le_32(IXGBE_TXD_STAT_DD))) { PMD_TX_FREE_LOG(DEBUG, "TX descriptor %4u is not done" @@ -806,12 +815,14 @@ ixgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, */ slen = m_seg->data_len; buf_dma_addr = RTE_MBUF_DATA_DMA_ADDR(m_seg); + txd->read.buffer_addr = rte_cpu_to_le_64(buf_dma_addr); txd->read.cmd_type_len = rte_cpu_to_le_32(cmd_type_len | slen); txd->read.olinfo_status = rte_cpu_to_le_32(olinfo_status); + txe->last_id = tx_last; tx_id = txe->next_id; txe = txn; @@ -1062,14 +1073,16 @@ ixgbe_rx_scan_hw_ring(struct ixgbe_rx_queue *rxq) int s[LOOK_AHEAD], nb_dd; #endif /* RTE_NEXT_ABI */ int i, j, nb_rx = 0; + uint32_t stat; /* get references to current descriptor and S/W ring entry */ rxdp = &rxq->rx_ring[rxq->rx_tail]; rxep = &rxq->sw_ring[rxq->rx_tail]; + stat = rxdp->wb.upper.status_error; /* check to make sure there is at least 1 packet to receive */ - if (! (rxdp->wb.upper.status_error & IXGBE_RXDADV_STAT_DD)) + if (!(stat & rte_cpu_to_le_32(IXGBE_RXDADV_STAT_DD))) return 0; /* @@ -1081,7 +1094,7 @@ ixgbe_rx_scan_hw_ring(struct ixgbe_rx_queue *rxq) { /* Read desc statuses backwards to avoid race condition */ for (j = LOOK_AHEAD-1; j >= 0; --j) - s[j] = rxdp[j].wb.upper.status_error; + s[j] = rte_le_to_cpu_32(rxdp[j].wb.upper.status_error); #ifdef RTE_NEXT_ABI for (j = LOOK_AHEAD - 1; j >= 0; --j) @@ -1099,7 +1112,9 @@ ixgbe_rx_scan_hw_ring(struct ixgbe_rx_queue *rxq) /* Translate descriptor info to mbuf format */ for (j = 0; j < nb_dd; ++j) { mb = rxep[j].mbuf; - pkt_len = (uint16_t)(rxdp[j].wb.upper.length - rxq->crc_len); + pkt_len = rte_le_to_cpu16(rxdp[j].wb.upper.length) - + rxq->crc_len; + mb->data_len = pkt_len; mb->pkt_len = pkt_len; mb->vlan_tci = rte_le_to_cpu_16(rxdp[j].wb.upper.vlan); @@ -1115,7 +1130,8 @@ ixgbe_rx_scan_hw_ring(struct ixgbe_rx_queue *rxq) ixgbe_rxd_pkt_info_to_pkt_type(pkt_info[j]); #else /* RTE_NEXT_ABI */ pkt_flags = rx_desc_hlen_type_rss_to_pkt_flags( - rxdp[j].wb.lower.lo_dword.data); + rte_le_to_cpu_32(rxdp[j].wb.lower.lo_dword.data)); + /* reuse status field from scan list */ pkt_flags |= rx_desc_status_to_pkt_flags(s[j]); pkt_flags |= rx_desc_error_to_pkt_flags(s[j]); @@ -1123,12 +1139,16 @@ ixgbe_rx_scan_hw_ring(struct ixgbe_rx_queue *rxq) #endif /* RTE_NEXT_ABI */ if (likely(pkt_flags & PKT_RX_RSS_HASH)) - mb->hash.rss = rxdp[j].wb.lower.hi_dword.rss; + mb->hash.rss = rte_le_to_cpu_32( + rxdp[j].wb.lower.hi_dword.rss); + else if (pkt_flags & PKT_RX_FDIR) { - mb->hash.fdir.hash = - (uint16_t)((rxdp[j].wb.lower.hi_dword.csum_ip.csum) - & IXGBE_ATR_HASH_MASK); - mb->hash.fdir.id = rxdp[j].wb.lower.hi_dword.csum_ip.ip_id; + mb->hash.fdir.hash = rte_le_to_cpu_16( + rxdp[j].wb.lower.hi_dword.csum_ip.csum) & + IXGBE_ATR_HASH_MASK; + + mb->hash.fdir.id = rte_le_to_cpu_16( + rxdp[j].wb.lower.hi_dword.csum_ip.ip_id); } } @@ -1365,7 +1385,7 @@ ixgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, */ rxdp = &rx_ring[rx_id]; staterr = rxdp->wb.upper.status_error; - if (! (staterr & rte_cpu_to_le_32(IXGBE_RXDADV_STAT_DD))) + if (!(staterr & rte_cpu_to_le_32(IXGBE_RXDADV_STAT_DD))) break; rxd = *rxdp; @@ -1483,12 +1503,15 @@ ixgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, #endif /* RTE_NEXT_ABI */ if (likely(pkt_flags & PKT_RX_RSS_HASH)) - rxm->hash.rss = rxd.wb.lower.hi_dword.rss; + rxm->hash.rss = rte_le_to_cpu_32( + rxd.wb.lower.hi_dword.rss); else if (pkt_flags & PKT_RX_FDIR) { - rxm->hash.fdir.hash = - (uint16_t)((rxd.wb.lower.hi_dword.csum_ip.csum) - & IXGBE_ATR_HASH_MASK); - rxm->hash.fdir.id = rxd.wb.lower.hi_dword.csum_ip.ip_id; + rxm->hash.fdir.hash = rte_le_to_cpu_16( + rxd.wb.lower.hi_dword.csum_ip.csum) & + IXGBE_ATR_HASH_MASK; + + rxm->hash.fdir.id = rte_le_to_cpu_16( + rxd.wb.lower.hi_dword.csum_ip.ip_id); } /* * Store the mbuf address into the next entry of the array @@ -1998,7 +2021,7 @@ ixgbe_reset_tx_queue(struct ixgbe_tx_queue *txq) prev = (uint16_t) (txq->nb_tx_desc - 1); for (i = 0; i < txq->nb_tx_desc; i++) { volatile union ixgbe_adv_tx_desc *txd = &txq->tx_ring[i]; - txd->wb.status = IXGBE_TXD_STAT_DD; + txd->wb.status = rte_cpu_to_le_32(IXGBE_TXD_STAT_DD); txe[i].mbuf = NULL; txe[i].last_id = i; txe[prev].next_id = i; @@ -2604,7 +2627,8 @@ ixgbe_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id) rxdp = &(rxq->rx_ring[rxq->rx_tail]); while ((desc < rxq->nb_rx_desc) && - (rxdp->wb.upper.status_error & IXGBE_RXDADV_STAT_DD)) { + (rxdp->wb.upper.status_error & + rte_cpu_to_le_32(IXGBE_RXDADV_STAT_DD))) { desc += IXGBE_RXQ_SCAN_INTERVAL; rxdp += IXGBE_RXQ_SCAN_INTERVAL; if (rxq->rx_tail + desc >= rxq->nb_rx_desc) @@ -2629,7 +2653,8 @@ ixgbe_dev_rx_descriptor_done(void *rx_queue, uint16_t offset) desc -= rxq->nb_rx_desc; rxdp = &rxq->rx_ring[desc]; - return !!(rxdp->wb.upper.status_error & IXGBE_RXDADV_STAT_DD); + return !!(rxdp->wb.upper.status_error & + rte_cpu_to_le_32(IXGBE_RXDADV_STAT_DD)); } void __attribute__((cold))