From patchwork Mon Jun 22 18:58:35 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Cyril Chemparathy X-Patchwork-Id: 5679 Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [IPv6:::1]) by dpdk.org (Postfix) with ESMTP id 5DF51C9AA; Mon, 22 Jun 2015 20:59:04 +0200 (CEST) Received: from sclab-apps-2.localdomain (sc-fw1.tilera.com [12.218.212.162]) by dpdk.org (Postfix) with ESMTP id 36216C902 for ; Mon, 22 Jun 2015 20:58:46 +0200 (CEST) X-CheckPoint: {55885AE5-C-A3D4DA0C-C0000002} Received: by sclab-apps-2.localdomain (Postfix, from userid 1318) id 8DEED2204F3; Mon, 22 Jun 2015 11:58:45 -0700 (PDT) From: Cyril Chemparathy To: dev@dpdk.org Date: Mon, 22 Jun 2015 11:58:35 -0700 Message-Id: <1434999524-26528-4-git-send-email-cchemparathy@ezchip.com> X-Mailer: git-send-email 2.1.2 In-Reply-To: <1434999524-26528-1-git-send-email-cchemparathy@ezchip.com> References: <1434999524-26528-1-git-send-email-cchemparathy@ezchip.com> Subject: [dpdk-dev] [PATCH v2 03/12] hash: check SSE flags only on x86 builds X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" This is necessary because the required CPU flags may not be defined on other architectures. Change-Id: I14d3f9f625b2e7567123f1c97095f8d06abd674b Signed-off-by: Cyril Chemparathy --- lib/librte_hash/rte_hash_crc.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/lib/librte_hash/rte_hash_crc.h b/lib/librte_hash/rte_hash_crc.h index abdbd9a..1f6f5bf 100644 --- a/lib/librte_hash/rte_hash_crc.h +++ b/lib/librte_hash/rte_hash_crc.h @@ -425,12 +425,14 @@ static inline void rte_hash_crc_set_alg(uint8_t alg) { switch (alg) { +#if defined(RTE_ARCH_I686) || defined(RTE_ARCH_X86_64) case CRC32_SSE42_x64: if (! rte_cpu_get_flag_enabled(RTE_CPUFLAG_EM64T)) alg = CRC32_SSE42; case CRC32_SSE42: if (! rte_cpu_get_flag_enabled(RTE_CPUFLAG_SSE4_2)) alg = CRC32_SW; +#endif case CRC32_SW: crc32_alg = alg; default: