From patchwork Fri Jun 5 23:15:09 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adrien Mazarguil X-Patchwork-Id: 5225 Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [IPv6:::1]) by dpdk.org (Postfix) with ESMTP id B12ABC3A0; Sat, 6 Jun 2015 01:15:59 +0200 (CEST) Received: from mail-wi0-f171.google.com (mail-wi0-f171.google.com [209.85.212.171]) by dpdk.org (Postfix) with ESMTP id 2000FC39C for ; Sat, 6 Jun 2015 01:15:58 +0200 (CEST) Received: by wiga1 with SMTP id a1so34701651wig.0 for ; Fri, 05 Jun 2015 16:15:58 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=D4PW+xK/ZH08pyxsKeHXIwWuUAqdxfjR/Vuu+eV/yiY=; b=fZ1qBn4vpRZxzk2URDqmGlsTqxHnOXepgYpIQCqwkWN9fm/Tk71HSI5kMQx8+Y6Ya4 MJ8WGWGjapMprUeO3pSwFZHWCRlL9rJ5GY5TFV0E52/yKwlycryT7PPoaucMyO2dGyMg ryXdjUNgjfPh7p+DNL7V5zjYAzrWHt7Aeua+Dz838QEVlep8Bs6W1y6Tb7G6qvAYB161 zLYgCoH1qRNmDUTtkdii8Eg/3gqjaXAaq0iHarwzAnAlgAeH2WjJb+uL6IGLCQ+4HOC4 gqzdNzzryToqDjxo31aDhz6FOuw5s/i859MKQw2LVaR/R87l5j1cIeKu9p7cDHcgjZs4 o4QA== X-Gm-Message-State: ALoCoQlBz+vo/+EDIIfOsg0aZ1PUrCUcKHUIHLCIbNLWqXs6KnzSMPxvLguO+ffh9lcY3kSpHSvj X-Received: by 10.180.104.167 with SMTP id gf7mr979259wib.3.1433546158016; Fri, 05 Jun 2015 16:15:58 -0700 (PDT) Received: from 6wind.com (guy78-3-82-239-227-177.fbx.proxad.net. [82.239.227.177]) by mx.google.com with ESMTPSA id ei8sm12615800wjd.32.2015.06.05.16.15.56 for (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Fri, 05 Jun 2015 16:15:57 -0700 (PDT) From: Adrien Mazarguil To: dev@dpdk.org Date: Sat, 6 Jun 2015 01:15:09 +0200 Message-Id: <1433546120-2254-6-git-send-email-adrien.mazarguil@6wind.com> X-Mailer: git-send-email 2.1.0 In-Reply-To: <1433546120-2254-1-git-send-email-adrien.mazarguil@6wind.com> References: <1433546120-2254-1-git-send-email-adrien.mazarguil@6wind.com> Subject: [dpdk-dev] [PATCH 05/16] mlx4: add L2 tunnel (VXLAN) RX checksum offload support X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Depending on adapters features and VXLAN support in the kernel, VXLAN frames can be automatically recognized, in which case checksum validation occurs on inner and outer L3 and L4. Signed-off-by: Adrien Mazarguil Acked-by: Guillaume Gaudonville --- drivers/net/mlx4/mlx4.c | 34 ++++++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/drivers/net/mlx4/mlx4.c b/drivers/net/mlx4/mlx4.c index cec894f..3210120 100644 --- a/drivers/net/mlx4/mlx4.c +++ b/drivers/net/mlx4/mlx4.c @@ -212,6 +212,7 @@ struct rxq { } elts; unsigned int sp:1; /* Use scattered RX elements. */ unsigned int csum:1; /* Enable checksum offloading. */ + unsigned int csum_l2tun:1; /* Same for L2 tunnels. */ uint32_t mb_len; /* Length of a mp-issued mbuf. */ struct mlx4_rxq_stats stats; /* RX queue counters. */ unsigned int socket; /* CPU socket ID for allocations. */ @@ -285,6 +286,7 @@ struct priv { unsigned int hw_tss:1; /* TSS is supported. */ unsigned int hw_rss:1; /* RSS is supported. */ unsigned int hw_csum:1; /* Checksum offload is supported. */ + unsigned int hw_csum_l2tun:1; /* Same for L2 tunnels. */ unsigned int rss:1; /* RSS is enabled. */ unsigned int vf:1; /* This is a VF device. */ #ifdef INLINE_RECV @@ -2329,6 +2331,25 @@ rxq_wc_to_ol_flags(const struct rxq *rxq, uint64_t exp_wc_flags) IBV_EXP_L3_RX_CSUM_OK, PKT_RX_IP_CKSUM_BAD) | TRANSPOSE(~exp_wc_flags, IBV_EXP_L4_RX_CSUM_OK, PKT_RX_L4_CKSUM_BAD); + /* + * PKT_RX_IP_CKSUM_BAD and PKT_RX_L4_CKSUM_BAD are used in place + * of PKT_RX_EIP_CKSUM_BAD because the latter is not functional + * (its value is 0). + */ + if ((exp_wc_flags & IBV_EXP_L2_TUNNEL_PACKET) && (rxq->csum_l2tun)) + ol_flags |= + TRANSPOSE(exp_wc_flags, + IBV_EXP_L2_TUNNEL_IPV4_PACKET, + PKT_RX_TUNNEL_IPV4_HDR) | + TRANSPOSE(exp_wc_flags, + IBV_EXP_L2_TUNNEL_IPV6_PACKET, + PKT_RX_TUNNEL_IPV6_HDR) | + TRANSPOSE(~exp_wc_flags, + IBV_EXP_L2_TUNNEL_L3_RX_CSUM_OK, + PKT_RX_IP_CKSUM_BAD) | + TRANSPOSE(~exp_wc_flags, + IBV_EXP_L2_TUNNEL_L4_RX_CSUM_OK, + PKT_RX_L4_CKSUM_BAD); return ol_flags; } @@ -2859,6 +2880,10 @@ rxq_rehash(struct rte_eth_dev *dev, struct rxq *rxq) tmpl.csum = !!dev->data->dev_conf.rxmode.hw_ip_checksum; rxq->csum = tmpl.csum; } + if (priv->hw_csum_l2tun) { + tmpl.csum_l2tun = !!dev->data->dev_conf.rxmode.hw_ip_checksum; + rxq->csum_l2tun = tmpl.csum_l2tun; + } /* Enable scattered packets support for this queue if necessary. */ if ((dev->data->dev_conf.rxmode.jumbo_frame) && (dev->data->dev_conf.rxmode.max_rx_pkt_len > @@ -3078,6 +3103,8 @@ rxq_setup(struct rte_eth_dev *dev, struct rxq *rxq, uint16_t desc, /* Toggle RX checksum offload if hardware supports it. */ if (priv->hw_csum) tmpl.csum = !!dev->data->dev_conf.rxmode.hw_ip_checksum; + if (priv->hw_csum_l2tun) + tmpl.csum_l2tun = !!dev->data->dev_conf.rxmode.hw_ip_checksum; /* Enable scattered packets support for this queue if necessary. */ if ((dev->data->dev_conf.rxmode.jumbo_frame) && (dev->data->dev_conf.rxmode.max_rx_pkt_len > @@ -4270,6 +4297,8 @@ static const struct eth_dev_ops mlx4_dev_ops = { .mac_addr_remove = mlx4_mac_addr_remove, .mac_addr_add = mlx4_mac_addr_add, .mtu_set = mlx4_dev_set_mtu, + .udp_tunnel_add = NULL, + .udp_tunnel_del = NULL, .fdir_add_signature_filter = NULL, .fdir_update_signature_filter = NULL, .fdir_remove_signature_filter = NULL, @@ -4599,6 +4628,11 @@ mlx4_pci_devinit(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev) DEBUG("checksum offloading is %ssupported", (priv->hw_csum ? "" : "not ")); + priv->hw_csum_l2tun = !!(exp_device_attr.exp_device_cap_flags & + IBV_EXP_DEVICE_L2_TUNNEL_OFFLOADS); + DEBUG("L2 tunnel checksum offloads are %ssupported", + (priv->hw_csum_l2tun ? "" : "not ")); + #ifdef INLINE_RECV priv->inl_recv_size = mlx4_getenv_int("MLX4_INLINE_RECV_SIZE");