From patchwork Fri May 29 08:10:39 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Chen, Jing D" X-Patchwork-Id: 4953 Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [IPv6:::1]) by dpdk.org (Postfix) with ESMTP id A5C439A8A; Fri, 29 May 2015 10:10:57 +0200 (CEST) Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by dpdk.org (Postfix) with ESMTP id CBF975A57 for ; Fri, 29 May 2015 10:10:55 +0200 (CEST) Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga103.fm.intel.com with ESMTP; 29 May 2015 01:10:54 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.13,515,1427785200"; d="scan'208";a="717419193" Received: from shvmail01.sh.intel.com ([10.239.29.42]) by fmsmga001.fm.intel.com with ESMTP; 29 May 2015 01:10:54 -0700 Received: from shecgisg003.sh.intel.com (shecgisg003.sh.intel.com [10.239.29.90]) by shvmail01.sh.intel.com with ESMTP id t4T8Aqr5010646; Fri, 29 May 2015 16:10:52 +0800 Received: from shecgisg003.sh.intel.com (localhost [127.0.0.1]) by shecgisg003.sh.intel.com (8.13.6/8.13.6/SuSE Linux 0.8) with ESMTP id t4T8AobP024818; Fri, 29 May 2015 16:10:52 +0800 Received: (from jingche2@localhost) by shecgisg003.sh.intel.com (8.13.6/8.13.6/Submit) id t4T8AnW6024814; Fri, 29 May 2015 16:10:49 +0800 From: "Chen Jing D(Mark)" To: dev@dpdk.org Date: Fri, 29 May 2015 16:10:39 +0800 Message-Id: <1432887044-24777-2-git-send-email-jing.d.chen@intel.com> X-Mailer: git-send-email 1.7.12.2 In-Reply-To: <1432887044-24777-1-git-send-email-jing.d.chen@intel.com> References: <1432887044-24777-1-git-send-email-jing.d.chen@intel.com> Cc: shaopeng.he@intel.com Subject: [dpdk-dev] [PATCH 1/6] fm10k: Fix improper RX buffer size assignment X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: "Chen Jing D(Mark)" As RX buffer is aligned to 512B within mbuf, some bytes are reserved for this purpose, and the worst case could be 511B. But SRR reg assumes all buffers have the same size. In order to fill the gap, we'll have to consider the worsst case and assume 512B is reserved. If we don't do so, it's possible for HW to overwrite data to next mbuf. Signed-off-by: Chen Jing D(Mark) Tested-by: Michael Qiu --- drivers/net/fm10k/fm10k.h | 5 +++-- drivers/net/fm10k/fm10k_ethdev.c | 12 ++++++++++-- 2 files changed, 13 insertions(+), 4 deletions(-) diff --git a/drivers/net/fm10k/fm10k.h b/drivers/net/fm10k/fm10k.h index 0e31796..ad7a7d1 100644 --- a/drivers/net/fm10k/fm10k.h +++ b/drivers/net/fm10k/fm10k.h @@ -191,7 +191,8 @@ struct fm10k_tx_queue { /* enforce 512B alignment on default Rx DMA addresses */ #define MBUF_DMA_ADDR_DEFAULT(mb) \ - ((uint64_t) RTE_ALIGN(((mb)->buf_physaddr + RTE_PKTMBUF_HEADROOM), 512)) + ((uint64_t) RTE_ALIGN(((mb)->buf_physaddr + RTE_PKTMBUF_HEADROOM),\ + FM10K_RX_DATABUF_ALIGN)) static inline void fifo_reset(struct fifo *fifo, uint32_t len) { @@ -263,7 +264,7 @@ fm10k_addr_alignment_valid(struct rte_mbuf *mb) uint64_t boundary1, boundary2; /* 512B aligned? */ - if (RTE_ALIGN(addr, 512) == addr) + if (RTE_ALIGN(addr, FM10K_RX_DATABUF_ALIGN) == addr) return 1; /* 8B aligned, and max Ethernet frame would not cross a 4KB boundary? */ diff --git a/drivers/net/fm10k/fm10k_ethdev.c b/drivers/net/fm10k/fm10k_ethdev.c index 275c19c..a5e09a0 100644 --- a/drivers/net/fm10k/fm10k_ethdev.c +++ b/drivers/net/fm10k/fm10k_ethdev.c @@ -41,7 +41,6 @@ #include "fm10k.h" #include "base/fm10k_api.h" -#define FM10K_RX_BUFF_ALIGN 512 /* Default delay to acquire mailbox lock */ #define FM10K_MBXLOCK_DELAY_US 20 #define UINT64_LOWER_32BITS_MASK 0x00000000ffffffffULL @@ -426,6 +425,15 @@ fm10k_dev_rx_init(struct rte_eth_dev *dev) /* Configure the Rx buffer size for one buff without split */ buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) - RTE_PKTMBUF_HEADROOM); + /* As RX buffer is aligned to 512B within mbuf, some bytes are + * reserved for this purpose, and the worst case could be 511B. + * But SRR reg assumes all buffers have the same size. In order + * to fill the gap, we'll have to consider the worst case and + * assume 512B is reserved. If we don't do so, it's possible + * for HW to overwrite data to next mbuf. + */ + buf_size -= FM10K_RX_DATABUF_ALIGN; + FM10K_WRITE_REG(hw, FM10K_SRRCTL(i), buf_size >> FM10K_SRRCTL_BSIZEPKT_SHIFT); @@ -909,7 +917,7 @@ mempool_element_size_valid(struct rte_mempool *mp) RTE_PKTMBUF_HEADROOM; /* account for up to 512B of alignment */ - min_size -= FM10K_RX_BUFF_ALIGN; + min_size -= FM10K_RX_DATABUF_ALIGN; /* sanity check for overflow */ if (min_size > mp->elt_size)