From patchwork Mon Apr 20 08:22:14 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Zhang, Helin" X-Patchwork-Id: 4361 Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [IPv6:::1]) by dpdk.org (Postfix) with ESMTP id D9639C392; Mon, 20 Apr 2015 10:22:48 +0200 (CEST) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by dpdk.org (Postfix) with ESMTP id C2D49C392 for ; Mon, 20 Apr 2015 10:22:46 +0200 (CEST) Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga102.fm.intel.com with ESMTP; 20 Apr 2015 01:22:45 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.11,608,1422950400"; d="scan'208";a="716179288" Received: from shvmail01.sh.intel.com ([10.239.29.42]) by orsmga002.jf.intel.com with ESMTP; 20 Apr 2015 01:22:44 -0700 Received: from shecgisg004.sh.intel.com (shecgisg004.sh.intel.com [10.239.29.89]) by shvmail01.sh.intel.com with ESMTP id t3K8Mco8013102; Mon, 20 Apr 2015 16:22:38 +0800 Received: from shecgisg004.sh.intel.com (localhost [127.0.0.1]) by shecgisg004.sh.intel.com (8.13.6/8.13.6/SuSE Linux 0.8) with ESMTP id t3K8MZlI028147; Mon, 20 Apr 2015 16:22:37 +0800 Received: (from hzhan75@localhost) by shecgisg004.sh.intel.com (8.13.6/8.13.6/Submit) id t3K8MZ5w028143; Mon, 20 Apr 2015 16:22:35 +0800 From: Helin Zhang To: dev@dpdk.org Date: Mon, 20 Apr 2015 16:22:14 +0800 Message-Id: <1429518150-28098-3-git-send-email-helin.zhang@intel.com> X-Mailer: git-send-email 1.7.4.1 In-Reply-To: <1429518150-28098-1-git-send-email-helin.zhang@intel.com> References: <1429518150-28098-1-git-send-email-helin.zhang@intel.com> Cc: monica.kenguva@intel.com, steven.j.murray@intel.com, chiu-pi.shih@intel.com Subject: [dpdk-dev] [PATCH 02/18] i40e: disable setting phy configuration X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" There was a known linke issue on 40G ports on NVM version (FVL3E), when setting phy configuration. As a workaround, setting phy configuration should be disabled. The impact is that the link cannot be forcedly configured, which doesn't affect any feature functions. The workaround can be removed when a formal fix is ready later. Signed-off-by: Helin Zhang --- lib/librte_pmd_i40e/i40e_ethdev.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/lib/librte_pmd_i40e/i40e_ethdev.c b/lib/librte_pmd_i40e/i40e_ethdev.c index df8686f..9fc2ee7 100644 --- a/lib/librte_pmd_i40e/i40e_ethdev.c +++ b/lib/librte_pmd_i40e/i40e_ethdev.c @@ -791,6 +791,10 @@ i40e_phy_conf_link(struct i40e_hw *hw, uint8_t abilities, uint8_t force_speed) I40E_LINK_SPEED_100MB; int ret = -ENOTSUP; + /* Skip it on 40G interfaces, as a workaround for the link issue */ + if (i40e_is_40G_device(hw->device_id)) + return I40E_SUCCESS; + status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab, NULL); if (status)