From patchwork Thu Feb 12 12:00:55 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ouyang Changchun X-Patchwork-Id: 3219 Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [IPv6:::1]) by dpdk.org (Postfix) with ESMTP id D8CC7ADAC; Thu, 12 Feb 2015 13:02:26 +0100 (CET) Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by dpdk.org (Postfix) with ESMTP id 8048FAD8E for ; Thu, 12 Feb 2015 13:02:20 +0100 (CET) Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga103.fm.intel.com with ESMTP; 12 Feb 2015 03:54:58 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.09,565,1418112000"; d="scan'208";a="651179436" Received: from shvmail01.sh.intel.com ([10.239.29.42]) by orsmga001.jf.intel.com with ESMTP; 12 Feb 2015 04:02:07 -0800 Received: from shecgisg004.sh.intel.com (shecgisg004.sh.intel.com [10.239.29.89]) by shvmail01.sh.intel.com with ESMTP id t1CC24qN012443; Thu, 12 Feb 2015 20:02:04 +0800 Received: from shecgisg004.sh.intel.com (localhost [127.0.0.1]) by shecgisg004.sh.intel.com (8.13.6/8.13.6/SuSE Linux 0.8) with ESMTP id t1CC20CZ030599; Thu, 12 Feb 2015 20:02:02 +0800 Received: (from couyang@localhost) by shecgisg004.sh.intel.com (8.13.6/8.13.6/Submit) id t1CC20he030595; Thu, 12 Feb 2015 20:02:00 +0800 From: Ouyang Changchun To: dev@dpdk.org Date: Thu, 12 Feb 2015 20:00:55 +0800 Message-Id: <1423742468-30404-24-git-send-email-changchun.ouyang@intel.com> X-Mailer: git-send-email 1.7.12.2 In-Reply-To: <1423742468-30404-1-git-send-email-changchun.ouyang@intel.com> References: <1423742468-30404-1-git-send-email-changchun.ouyang@intel.com> Subject: [dpdk-dev] [PATCH 23/36] ixgbe base codes: API for write i2c combined X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" New API to perform I2C write combined operation. Signed-off-by: Changchun Ouyang --- lib/librte_pmd_ixgbe/ixgbe/ixgbe_api.c | 16 ++++++++++++++++ lib/librte_pmd_ixgbe/ixgbe/ixgbe_api.h | 1 + lib/librte_pmd_ixgbe/ixgbe/ixgbe_x550.c | 11 +++++++++-- 3 files changed, 26 insertions(+), 2 deletions(-) diff --git a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_api.c b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_api.c index ae13adb..8037301 100644 --- a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_api.c +++ b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_api.c @@ -1326,6 +1326,7 @@ s32 ixgbe_read_i2c_combined(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 *val) * ixgbe_write_i2c_byte - Writes 8 bit word over I2C * @hw: pointer to hardware structure * @byte_offset: byte offset to write + * @dev_addr: I2C bus address to write to * @data: value to write * * Performs byte write operation to SFP module's EEPROM over I2C interface @@ -1339,6 +1340,21 @@ s32 ixgbe_write_i2c_byte(struct ixgbe_hw *hw, u8 byte_offset, u8 dev_addr, } /** + * ixgbe_write_i2c_combined - Perform I2C write combined operation + * @hw: pointer to the hardware structure + * @addr: I2C bus address to write to + * @reg: I2C device register to write to + * @val: value to write + * + * Returns an error code on error. + */ +s32 ixgbe_write_i2c_combined(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 val) +{ + return ixgbe_call_func(hw, hw->phy.ops.write_i2c_combined, (hw, addr, + reg, val), IXGBE_NOT_IMPLEMENTED); +} + +/** * ixgbe_write_i2c_eeprom - Writes 8 bit EEPROM word over I2C interface * @hw: pointer to hardware structure * @byte_offset: EEPROM byte offset to write diff --git a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_api.h b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_api.h index 77ebc64..8386e29 100644 --- a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_api.h +++ b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_api.h @@ -174,6 +174,7 @@ s32 ixgbe_read_i2c_byte(struct ixgbe_hw *hw, u8 byte_offset, u8 dev_addr, s32 ixgbe_read_i2c_combined(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 *val); s32 ixgbe_write_i2c_byte(struct ixgbe_hw *hw, u8 byte_offset, u8 dev_addr, u8 data); +s32 ixgbe_write_i2c_combined(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 val); s32 ixgbe_write_i2c_eeprom(struct ixgbe_hw *hw, u8 byte_offset, u8 eeprom_data); s32 ixgbe_get_san_mac_addr(struct ixgbe_hw *hw, u8 *san_mac_addr); s32 ixgbe_set_san_mac_addr(struct ixgbe_hw *hw, u8 *san_mac_addr); diff --git a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_x550.c b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_x550.c index d8a0c19..bdf41da 100644 --- a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_x550.c +++ b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_x550.c @@ -787,6 +787,7 @@ s32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw) { bool setup_linear; u16 reg_slice, edc_mode; + s32 ret_val; DEBUGFUNC("ixgbe_setup_sfp_modules_X550em"); @@ -827,8 +828,14 @@ s32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw) edc_mode = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1; /* Configure CS4227 for connection type. */ - return hw->phy.ops.write_i2c_combined(hw, IXGBE_CS4227, - reg_slice, edc_mode); + ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice, + edc_mode); + + if (ret_val != IXGBE_SUCCESS) + ret_val = ixgbe_write_i2c_combined(hw, 0x80, reg_slice, + edc_mode); + + return ret_val; } /**