From patchwork Mon Dec 8 08:59:26 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhigang Lu X-Patchwork-Id: 1804 Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [IPv6:::1]) by dpdk.org (Postfix) with ESMTP id A1393803D; Mon, 8 Dec 2014 10:20:53 +0100 (CET) Received: from emea01-db3-obe.outbound.protection.outlook.com (mail-db3on0053.outbound.protection.outlook.com [157.55.234.53]) by dpdk.org (Postfix) with ESMTP id C7E5ECE7 for ; Mon, 8 Dec 2014 10:00:35 +0100 (CET) Received: from DB4PR02CA0016.eurprd02.prod.outlook.com (10.242.174.144) by AMSPR02MB006.eurprd02.prod.outlook.com (10.242.89.154) with Microsoft SMTP Server (TLS) id 15.1.26.15; Mon, 8 Dec 2014 09:00:33 +0000 Received: from DB3FFO11FD040.protection.gbl (2a01:111:f400:7e04::147) by DB4PR02CA0016.outlook.office365.com (2a01:111:e400:983b::16) with Microsoft SMTP Server (TLS) id 15.1.31.17 via Frontend Transport; Mon, 8 Dec 2014 09:00:33 +0000 Received: from bjgfarm-1.internal.tilera.com (124.207.145.166) by DB3FFO11FD040.mail.protection.outlook.com (10.47.217.71) with Microsoft SMTP Server (TLS) id 15.1.26.17 via Frontend Transport; Mon, 8 Dec 2014 09:00:32 +0000 Received: (from zlu@localhost) by bjgfarm-1.internal.tilera.com (8.14.4/8.14.4/Submit) id sB890Rsb025232; Mon, 8 Dec 2014 17:00:27 +0800 From: Zhigang Lu To: Date: Mon, 8 Dec 2014 16:59:26 +0800 Message-ID: <1418029178-25162-4-git-send-email-zlu@ezchip.com> X-Mailer: git-send-email 2.1.2 In-Reply-To: <1418029178-25162-1-git-send-email-zlu@ezchip.com> References: <1418029178-25162-1-git-send-email-zlu@ezchip.com> X-EOPAttributedMessage: 0 X-Forefront-Antispam-Report: CIP:124.207.145.166; CTRY:CN; IPV:NLI; EFV:NLI; SFV:NSPM; SFS:(10009020)(6009001)(189002)(199003)(120916001)(31966008)(97736003)(47776003)(50986999)(42186005)(46102003)(76176999)(64706001)(86362001)(92566001)(20776003)(19580395003)(19580405001)(6806004)(87936001)(105606002)(50466002)(106466001)(104016003)(33646002)(107046002)(99396003)(48376002)(21056001)(110136001)(84676001)(62966003)(4396001)(89996001)(36756003)(77156002)(2351001)(50226001)(229853001)(68736005)(9376004); DIR:OUT; SFP:1101; SCL:1; SRVR:AMSPR02MB006; H:bjgfarm-1.internal.tilera.com; FPR:; SPF:Fail; MLV:sfv; PTR:InfoDomainNonexistent; MX:1; A:1; LANG:en; MIME-Version: 1.0 X-Microsoft-Antispam: UriScan:; X-Microsoft-Antispam: BCL:0;PCL:0;RULEID:;SRVR:AMSPR02MB006; X-Exchange-Antispam-Report-Test: UriScan:; X-Exchange-Antispam-Report-CFA-Test: BCL:0; PCL:0; RULEID:(602002); SRVR:AMSPR02MB006; X-Forefront-PRVS: 041963B986 Received-SPF: Fail (protection.outlook.com: domain of ezchip.com does not designate 124.207.145.166 as permitted sender) receiver=protection.outlook.com; client-ip=124.207.145.166; helo=bjgfarm-1.internal.tilera.com; Authentication-Results: spf=fail (sender IP is 124.207.145.166) smtp.mailfrom=zlu@ezchip.com; X-Exchange-Antispam-Report-CFA-Test: BCL:0;PCL:0;RULEID:;SRVR:AMSPR02MB006; X-OriginatorOrg: ezchip.com X-Mailman-Approved-At: Mon, 08 Dec 2014 10:20:50 +0100 Cc: Cyril Chemparathy Subject: [dpdk-dev] [PATCH 03/15] eal/tile: add byte order operations for TileGx X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" This patch adds architecture specific byte swap and endianness operations for TileGx. Signed-off-by: Zhigang Lu Signed-off-by: Cyril Chemparathy --- .../common/include/arch/tile/rte_byteorder.h | 70 ++++++++++++++++++++++ 1 file changed, 70 insertions(+) create mode 100644 lib/librte_eal/common/include/arch/tile/rte_byteorder.h diff --git a/lib/librte_eal/common/include/arch/tile/rte_byteorder.h b/lib/librte_eal/common/include/arch/tile/rte_byteorder.h new file mode 100644 index 0000000..38f3a23 --- /dev/null +++ b/lib/librte_eal/common/include/arch/tile/rte_byteorder.h @@ -0,0 +1,70 @@ +/*- + * BSD LICENSE + * + * Copyright(c) 2014 Tilera Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Tilera Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _RTE_BYTEORDER_TILE_H_ +#define _RTE_BYTEORDER_TILE_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "generic/rte_byteorder.h" + +/* + * __builtin_bswap16 is only available gcc 4.8 and upwards + */ +#if __GNUC__ < 4 || (__GNUC__ == 4 && __GNUC_MINOR__ < 8) +#define rte_bswap16(x) ((uint16_t)rte_constant_bswap16(x)) +#endif + +#define rte_cpu_to_le_16(x) (x) +#define rte_cpu_to_le_32(x) (x) +#define rte_cpu_to_le_64(x) (x) + +#define rte_cpu_to_be_16(x) rte_bswap16(x) +#define rte_cpu_to_be_32(x) rte_bswap32(x) +#define rte_cpu_to_be_64(x) rte_bswap64(x) + +#define rte_le_to_cpu_16(x) (x) +#define rte_le_to_cpu_32(x) (x) +#define rte_le_to_cpu_64(x) (x) + +#define rte_be_to_cpu_16(x) rte_bswap16(x) +#define rte_be_to_cpu_32(x) rte_bswap32(x) +#define rte_be_to_cpu_64(x) rte_bswap64(x) + +#ifdef __cplusplus +} +#endif + +#endif /* _RTE_BYTEORDER_TILE_H_ */