From patchwork Mon Nov 17 04:48:25 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chao Zhu X-Patchwork-Id: 1311 Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [IPv6:::1]) by dpdk.org (Postfix) with ESMTP id B35E88037; Sun, 16 Nov 2014 17:38:02 +0100 (CET) Received: from e28smtp07.in.ibm.com (e28smtp07.in.ibm.com [122.248.162.7]) by dpdk.org (Postfix) with ESMTP id 8DC037EF3 for ; Sun, 16 Nov 2014 17:37:41 +0100 (CET) Received: from /spool/local by e28smtp07.in.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Sun, 16 Nov 2014 22:17:53 +0530 Received: from d28dlp03.in.ibm.com (9.184.220.128) by e28smtp07.in.ibm.com (192.168.1.137) with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted; Sun, 16 Nov 2014 22:17:50 +0530 Received: from d28relay02.in.ibm.com (d28relay02.in.ibm.com [9.184.220.59]) by d28dlp03.in.ibm.com (Postfix) with ESMTP id 35C9B1258044 for ; Sun, 16 Nov 2014 22:17:56 +0530 (IST) Received: from d28av01.in.ibm.com (d28av01.in.ibm.com [9.184.220.63]) by d28relay02.in.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id sAGGm50E46268416 for ; Sun, 16 Nov 2014 22:18:05 +0530 Received: from d28av01.in.ibm.com (localhost [127.0.0.1]) by d28av01.in.ibm.com (8.14.4/8.14.4/NCO v10.0 AVout) with ESMTP id sAGGlnk5032043 for ; Sun, 16 Nov 2014 22:17:49 +0530 Received: from os_controller.crl.ibm.com ([9.186.57.97]) by d28av01.in.ibm.com (8.14.4/8.14.4/NCO v10.0 AVin) with ESMTP id sAGGlP3D029091 for ; Sun, 16 Nov 2014 22:17:49 +0530 From: Chao Zhu To: dev@dpdk.org Date: Sun, 16 Nov 2014 23:48:25 -0500 Message-Id: <1416199705-24150-13-git-send-email-chaozhu@linux.vnet.ibm.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1416199705-24150-1-git-send-email-chaozhu@linux.vnet.ibm.com> References: <1416199705-24150-1-git-send-email-chaozhu@linux.vnet.ibm.com> X-TM-AS-MML: disable X-Content-Scanned: Fidelis XPS MAILER x-cbid: 14111616-0025-0000-0000-000001E56EB4 Subject: [dpdk-dev] [PATCH v2 12/12] Add eal memory support for IBM Power Architecture X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" IBM Power architecture has different memory architecture with x86. When the physical memory address is in ascending order, the mmaped virtual address is in descending order. This patch modified the memory segment detection code to make it work for Power. This patch also added a commond ARCH_PPC_64 defination for 64 bit systems. Signed-off-by: Chao Zhu --- config/defconfig_ppc_64-power8-linuxapp-gcc | 1 + config/defconfig_x86_64-native-linuxapp-clang | 1 + config/defconfig_x86_64-native-linuxapp-gcc | 1 + config/defconfig_x86_64-native-linuxapp-icc | 1 + lib/librte_eal/linuxapp/eal/eal_memory.c | 27 +++++++++++++++++++----- 5 files changed, 25 insertions(+), 6 deletions(-) diff --git a/config/defconfig_ppc_64-power8-linuxapp-gcc b/config/defconfig_ppc_64-power8-linuxapp-gcc index b10f60c..23a5591 100644 --- a/config/defconfig_ppc_64-power8-linuxapp-gcc +++ b/config/defconfig_ppc_64-power8-linuxapp-gcc @@ -35,6 +35,7 @@ CONFIG_RTE_MACHINE="power8" CONFIG_RTE_ARCH="ppc_64" CONFIG_RTE_ARCH_PPC_64=y CONFIG_RTE_ARCH_BIG_ENDIAN=y +CONFIG_RTE_ARCH_64=y CONFIG_RTE_TOOLCHAIN="gcc" CONFIG_RTE_TOOLCHAIN_GCC=y diff --git a/config/defconfig_x86_64-native-linuxapp-clang b/config/defconfig_x86_64-native-linuxapp-clang index bbda080..5f3074e 100644 --- a/config/defconfig_x86_64-native-linuxapp-clang +++ b/config/defconfig_x86_64-native-linuxapp-clang @@ -36,6 +36,7 @@ CONFIG_RTE_MACHINE="native" CONFIG_RTE_ARCH="x86_64" CONFIG_RTE_ARCH_X86_64=y +CONFIG_RTE_ARCH_64=y CONFIG_RTE_TOOLCHAIN="clang" CONFIG_RTE_TOOLCHAIN_CLANG=y diff --git a/config/defconfig_x86_64-native-linuxapp-gcc b/config/defconfig_x86_64-native-linuxapp-gcc index 3de818a..60baf5b 100644 --- a/config/defconfig_x86_64-native-linuxapp-gcc +++ b/config/defconfig_x86_64-native-linuxapp-gcc @@ -36,6 +36,7 @@ CONFIG_RTE_MACHINE="native" CONFIG_RTE_ARCH="x86_64" CONFIG_RTE_ARCH_X86_64=y +CONFIG_RTE_ARCH_64=y CONFIG_RTE_TOOLCHAIN="gcc" CONFIG_RTE_TOOLCHAIN_GCC=y diff --git a/config/defconfig_x86_64-native-linuxapp-icc b/config/defconfig_x86_64-native-linuxapp-icc index 795333b..71d1e28 100644 --- a/config/defconfig_x86_64-native-linuxapp-icc +++ b/config/defconfig_x86_64-native-linuxapp-icc @@ -36,6 +36,7 @@ CONFIG_RTE_MACHINE="native" CONFIG_RTE_ARCH="x86_64" CONFIG_RTE_ARCH_X86_64=y +CONFIG_RTE_ARCH_64=y CONFIG_RTE_TOOLCHAIN="icc" CONFIG_RTE_TOOLCHAIN_ICC=y diff --git a/lib/librte_eal/linuxapp/eal/eal_memory.c b/lib/librte_eal/linuxapp/eal/eal_memory.c index f2454f4..b9c6d2e 100644 --- a/lib/librte_eal/linuxapp/eal/eal_memory.c +++ b/lib/librte_eal/linuxapp/eal/eal_memory.c @@ -316,11 +316,11 @@ map_all_hugepages(struct hugepage_file *hugepg_tbl, #endif hugepg_tbl[i].filepath[sizeof(hugepg_tbl[i].filepath) - 1] = '\0'; } -#ifndef RTE_ARCH_X86_64 - /* for 32-bit systems, don't remap 1G pages, just reuse original +#ifndef RTE_ARCH_64 + /* for 32-bit systems, don't remap 1G and 16G pages, just reuse original * map address as final map address. */ - else if (hugepage_sz == RTE_PGSIZE_1G){ + else if ((hugepage_sz == RTE_PGSIZE_1G) || (hugepage_sz == RTE_PGSIZE_16G)){ hugepg_tbl[i].final_va = hugepg_tbl[i].orig_va; hugepg_tbl[i].orig_va = NULL; continue; @@ -412,11 +412,11 @@ remap_all_hugepages(struct hugepage_file *hugepg_tbl, struct hugepage_info *hpi) while (i < hpi->num_pages[0]) { -#ifndef RTE_ARCH_X86_64 - /* for 32-bit systems, don't remap 1G pages, just reuse original +#ifndef RTE_ARCH_64 + /* for 32-bit systems, don't remap 1G pages and 16G pages, just reuse original * map address as final map address. */ - if (hugepage_sz == RTE_PGSIZE_1G){ + if ((hugepage_sz == RTE_PGSIZE_1G) || (hugepage_sz == RTE_PGSIZE_16G)){ hugepg_tbl[i].final_va = hugepg_tbl[i].orig_va; hugepg_tbl[i].orig_va = NULL; i++; @@ -1263,9 +1263,18 @@ rte_eal_hugepage_init(void) else if ((hugepage[i].physaddr - hugepage[i-1].physaddr) != hugepage[i].size) new_memseg = 1; +#ifdef RTE_ARCH_PPC_64 + /* IBM Power architecture has different memory layout than x86. + * If the physical address is lower address first, the mmaped virtual + * address will be higher address first */ + else if (((unsigned long)hugepage[i-1].final_va - + (unsigned long)hugepage[i].final_va) != hugepage[i].size) + new_memseg = 1; +#else else if (((unsigned long)hugepage[i].final_va - (unsigned long)hugepage[i-1].final_va) != hugepage[i].size) new_memseg = 1; +#endif if (new_memseg) { j += 1; @@ -1284,6 +1293,12 @@ rte_eal_hugepage_init(void) } /* continuation of previous memseg */ else { +#ifdef RTE_ARCH_PPC_64 + /* Use the phy and virt address of the last page as segment address + * for IBM Power architecture */ + mcfg->memseg[j].phys_addr = hugepage[i].physaddr; + mcfg->memseg[j].addr = hugepage[i].final_va; +#endif mcfg->memseg[j].len += mcfg->memseg[j].hugepage_sz; } hugepage[i].memseg_id = j;