From patchwork Wed Oct 22 01:01:23 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jingjing Wu X-Patchwork-Id: 906 Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [IPv6:::1]) by dpdk.org (Postfix) with ESMTP id 37BE27F11; Wed, 22 Oct 2014 02:54:30 +0200 (CEST) Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by dpdk.org (Postfix) with ESMTP id C22BD7E80 for ; Wed, 22 Oct 2014 02:54:16 +0200 (CEST) Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga103.fm.intel.com with ESMTP; 21 Oct 2014 17:56:52 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="4.97,862,1389772800"; d="scan'208";a="403849676" Received: from shvmail01.sh.intel.com ([10.239.29.42]) by FMSMGA003.fm.intel.com with ESMTP; 21 Oct 2014 17:54:51 -0700 Received: from shecgisg004.sh.intel.com (shecgisg004.sh.intel.com [10.239.29.89]) by shvmail01.sh.intel.com with ESMTP id s9M12Qib010401; Wed, 22 Oct 2014 09:02:26 +0800 Received: from shecgisg004.sh.intel.com (localhost [127.0.0.1]) by shecgisg004.sh.intel.com (8.13.6/8.13.6/SuSE Linux 0.8) with ESMTP id s9M12Om5011331; Wed, 22 Oct 2014 09:02:26 +0800 Received: (from wujingji@localhost) by shecgisg004.sh.intel.com (8.13.6/8.13.6/Submit) id s9M12OVm011327; Wed, 22 Oct 2014 09:02:24 +0800 From: Jingjing Wu To: dev@dpdk.org Date: Wed, 22 Oct 2014 09:01:23 +0800 Message-Id: <1413939687-11177-18-git-send-email-jingjing.wu@intel.com> X-Mailer: git-send-email 1.7.4.1 In-Reply-To: <1413939687-11177-1-git-send-email-jingjing.wu@intel.com> References: <1411711418-12881-1-git-send-email-jingjing.wu@intel.com> <1413939687-11177-1-git-send-email-jingjing.wu@intel.com> Subject: [dpdk-dev] [PATCH v4 17/21] i40e: implement operations to configure flexible payload X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" implement operation to flexible payload in i40e pmd driver Signed-off-by: Jingjing Wu --- lib/librte_pmd_i40e/i40e_fdir.c | 106 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 106 insertions(+) diff --git a/lib/librte_pmd_i40e/i40e_fdir.c b/lib/librte_pmd_i40e/i40e_fdir.c index 00ee470..67498ff 100644 --- a/lib/librte_pmd_i40e/i40e_fdir.c +++ b/lib/librte_pmd_i40e/i40e_fdir.c @@ -83,6 +83,8 @@ #define I40E_FLX_OFFSET_IN_FIELD_VECTOR 50 static int i40e_fdir_rx_queue_init(struct i40e_rx_queue *rxq); +static int i40e_set_flx_pld_cfg(struct i40e_pf *pf, + struct rte_eth_flex_payload_cfg *cfg); static int i40e_fdir_construct_pkt(struct i40e_pf *pf, struct rte_eth_fdir_input *fdir_input, unsigned char *raw_pkt); @@ -327,6 +329,98 @@ i40e_fdir_teardown(struct i40e_pf *pf) } /* + * i40e_set_flx_pld_cfg -configure the rule how bytes stream is extracted as flexible payload + * @pf: board private structure + * @cfg: the rule how bytes stream is extracted as flexible payload + */ +static int +i40e_set_flx_pld_cfg(struct i40e_pf *pf, + struct rte_eth_flex_payload_cfg *cfg) +{ + struct i40e_hw *hw = I40E_PF_TO_HW(pf); + struct rte_eth_fdir_info fdir; + uint32_t flx_pit; + uint16_t min_next_off = 0; + uint8_t idx = 0; + int i = 0; + int num_word = 0; + int ret; + + if (cfg == NULL || cfg->nb_field > 3) + return -EINVAL; + + if (cfg->type == RTE_ETH_L2_PAYLOAD) + idx = 0; + else if (cfg->type == RTE_ETH_L3_PAYLOAD) + idx = 1; + else if (cfg->type == RTE_ETH_L4_PAYLOAD) + idx = 2; + else { + PMD_DRV_LOG(ERR, "unknown payload type."); + return -EINVAL; + } + /* + * flexible payload need to be configured before + * flow director filters are added + * If filters exist, flush them. + */ + memset(&fdir, 0, sizeof(fdir)); + i40e_fdir_info_get(pf, &fdir); + if (fdir.info_ext.best_cnt + fdir.info_ext.guarant_cnt > 0) { + ret = i40e_fdir_flush(pf); + if (ret) { + PMD_DRV_LOG(ERR, " failed to flush fdir table."); + return ret; + } + } + + for (i = 0; i < cfg->nb_field; i++) { + /* + * check register's constrain + * Current Offset >= previous offset + previous FSIZE. + */ + if (cfg->field[i].offset < min_next_off) { + PMD_DRV_LOG(ERR, "Offset should be larger than" + "previous offset + previous FSIZE."); + return -EINVAL; + } + flx_pit = (cfg->field[i].offset << + I40E_PRTQF_FLX_PIT_SOURCE_OFF_SHIFT) & + I40E_PRTQF_FLX_PIT_SOURCE_OFF_MASK; + flx_pit |= (cfg->field[i].size << + I40E_PRTQF_FLX_PIT_FSIZE_SHIFT) & + I40E_PRTQF_FLX_PIT_FSIZE_MASK; + flx_pit |= ((num_word + I40E_FLX_OFFSET_IN_FIELD_VECTOR) << + I40E_PRTQF_FLX_PIT_DEST_OFF_SHIFT) & + I40E_PRTQF_FLX_PIT_DEST_OFF_MASK; + /* support no more than 8 words flexible payload*/ + num_word += cfg->field[i].size; + if (num_word > 8) + return -EINVAL; + + I40E_WRITE_REG(hw, I40E_PRTQF_FLX_PIT(idx * 3 + i), flx_pit); + /* record the info in fdir structure */ + pf->fdir.flex_set[idx][i].offset = cfg->field[i].offset; + pf->fdir.flex_set[idx][i].size = cfg->field[i].size; + min_next_off = cfg->field[i].offset + cfg->field[i].size; + } + + for (; i < 3; i++) { + /* set the non-used register obeying register's constrain */ + flx_pit = (min_next_off << I40E_PRTQF_FLX_PIT_SOURCE_OFF_SHIFT) & + I40E_PRTQF_FLX_PIT_SOURCE_OFF_MASK; + flx_pit |= (1 << I40E_PRTQF_FLX_PIT_FSIZE_SHIFT) & + I40E_PRTQF_FLX_PIT_FSIZE_MASK; + flx_pit |= (63 << I40E_PRTQF_FLX_PIT_DEST_OFF_SHIFT) & + I40E_PRTQF_FLX_PIT_DEST_OFF_MASK; + I40E_WRITE_REG(hw, I40E_PRTQF_FLX_PIT(idx * 3 + i), flx_pit); + min_next_off++; + } + + return 0; +} + +/* * i40e_fdir_construct_pkt - construct packet based on fields in input * @pf: board private structure * @fdir_input: input set of the flow director entry @@ -958,6 +1052,7 @@ i40e_fdir_info_get(struct i40e_pf *pf, struct rte_eth_fdir_info *fdir) int i40e_fdir_ctrl_func(struct i40e_pf *pf, enum rte_filter_op filter_op, void *arg) { + struct rte_eth_fdir_cfg *fdir_cfg = NULL; int ret = 0; if (arg == NULL && filter_op != RTE_ETH_FILTER_NOP && @@ -982,6 +1077,17 @@ i40e_fdir_ctrl_func(struct i40e_pf *pf, enum rte_filter_op filter_op, void *arg) case RTE_ETH_FILTER_FLUSH: ret = i40e_fdir_flush(pf); break; + case RTE_ETH_FILTER_SET: + fdir_cfg = (struct rte_eth_fdir_cfg *)arg; + if (fdir_cfg->cmd == RTE_ETH_FDIR_CFG_FLX) + ret = i40e_set_flx_pld_cfg(pf, + (struct rte_eth_flex_payload_cfg *)fdir_cfg->cfg); + else { + PMD_DRV_LOG(WARNING, "unsupported configuration command %u.", + fdir_cfg->cmd); + return -EINVAL; + } + break; case RTE_ETH_FILTER_INFO: i40e_fdir_info_get(pf, (struct rte_eth_fdir_info *)arg); break;