From patchwork Tue Oct 21 03:14:47 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Zhang, Helin" X-Patchwork-Id: 871 Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [IPv6:::1]) by dpdk.org (Postfix) with ESMTP id 278287E95; Tue, 21 Oct 2014 05:08:15 +0200 (CEST) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by dpdk.org (Postfix) with ESMTP id 8746F7E7A for ; Tue, 21 Oct 2014 05:08:12 +0200 (CEST) Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga101.fm.intel.com with ESMTP; 20 Oct 2014 20:15:54 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.04,759,1406617200"; d="scan'208";a="617620111" Received: from shvmail01.sh.intel.com ([10.239.29.42]) by fmsmga002.fm.intel.com with ESMTP; 20 Oct 2014 20:15:08 -0700 Received: from shecgisg004.sh.intel.com (shecgisg004.sh.intel.com [10.239.29.89]) by shvmail01.sh.intel.com with ESMTP id s9L3F7LX014809; Tue, 21 Oct 2014 11:15:07 +0800 Received: from shecgisg004.sh.intel.com (localhost [127.0.0.1]) by shecgisg004.sh.intel.com (8.13.6/8.13.6/SuSE Linux 0.8) with ESMTP id s9L3F5uZ026762; Tue, 21 Oct 2014 11:15:07 +0800 Received: (from hzhan75@localhost) by shecgisg004.sh.intel.com (8.13.6/8.13.6/Submit) id s9L3F4qJ026758; Tue, 21 Oct 2014 11:15:04 +0800 From: Helin Zhang To: dev@dpdk.org Date: Tue, 21 Oct 2014 11:14:47 +0800 Message-Id: <1413861289-26662-4-git-send-email-helin.zhang@intel.com> X-Mailer: git-send-email 1.7.4.1 In-Reply-To: <1413861289-26662-1-git-send-email-helin.zhang@intel.com> References: <1413180766-12211-1-git-send-email-helin.zhang@intel.com> <1413861289-26662-1-git-send-email-helin.zhang@intel.com> Subject: [dpdk-dev] [PATCH v5 3/5] i40e: add hash filter control implementation X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Hash filter control has been implemented for i40e. It includes getting/setting, - hash function type - symmetric hash enable per pctype (packet classification type) - symmetric hash enable per port - filter swap configuration Signed-off-by: Helin Zhang --- lib/librte_pmd_i40e/i40e_ethdev.c | 377 +++++++++++++++++++++++++++++++++++++- 1 file changed, 375 insertions(+), 2 deletions(-) v5 changes: * Integrated with filter API defined recently. diff --git a/lib/librte_pmd_i40e/i40e_ethdev.c b/lib/librte_pmd_i40e/i40e_ethdev.c index 5e5cfbe..7531e3c 100644 --- a/lib/librte_pmd_i40e/i40e_ethdev.c +++ b/lib/librte_pmd_i40e/i40e_ethdev.c @@ -4145,6 +4145,378 @@ i40e_pf_config_mq_rx(struct i40e_pf *pf) return 0; } +/* Get the symmetric hash enable configurations per PCTYPE */ +static int +i40e_get_symmetric_hash_enable_per_pctype(struct i40e_hw *hw, + struct rte_eth_sym_hash_ena_info *info) +{ + uint32_t reg; + + switch (info->pctype) { + case ETH_RSS_NONF_IPV4_UDP_SHIFT: + case ETH_RSS_NONF_IPV4_TCP_SHIFT: + case ETH_RSS_NONF_IPV4_SCTP_SHIFT: + case ETH_RSS_NONF_IPV4_OTHER_SHIFT: + case ETH_RSS_FRAG_IPV4_SHIFT: + case ETH_RSS_NONF_IPV6_UDP_SHIFT: + case ETH_RSS_NONF_IPV6_TCP_SHIFT: + case ETH_RSS_NONF_IPV6_SCTP_SHIFT: + case ETH_RSS_NONF_IPV6_OTHER_SHIFT: + case ETH_RSS_FRAG_IPV6_SHIFT: + case ETH_RSS_L2_PAYLOAD_SHIFT: + reg = I40E_READ_REG(hw, I40E_GLQF_HSYM(info->pctype)); + info->enable = reg & I40E_GLQF_HSYM_SYMH_ENA_MASK ? 1 : 0; + break; + default: + PMD_DRV_LOG(ERR, "PCTYPE[%u] not supported", info->pctype); + return -EINVAL; + } + + return 0; +} + +/* Set the symmetric hash enable configurations per PCTYPE */ +static int +i40e_set_symmetric_hash_enable_per_pctype(struct i40e_hw *hw, + const struct rte_eth_sym_hash_ena_info *info) +{ + uint32_t reg; + + switch (info->pctype) { + case ETH_RSS_NONF_IPV4_UDP_SHIFT: + case ETH_RSS_NONF_IPV4_TCP_SHIFT: + case ETH_RSS_NONF_IPV4_SCTP_SHIFT: + case ETH_RSS_NONF_IPV4_OTHER_SHIFT: + case ETH_RSS_FRAG_IPV4_SHIFT: + case ETH_RSS_NONF_IPV6_UDP_SHIFT: + case ETH_RSS_NONF_IPV6_TCP_SHIFT: + case ETH_RSS_NONF_IPV6_SCTP_SHIFT: + case ETH_RSS_NONF_IPV6_OTHER_SHIFT: + case ETH_RSS_FRAG_IPV6_SHIFT: + case ETH_RSS_L2_PAYLOAD_SHIFT: + reg = info->enable ? I40E_GLQF_HSYM_SYMH_ENA_MASK : 0; + I40E_WRITE_REG(hw, I40E_GLQF_HSYM(info->pctype), reg); + I40E_WRITE_FLUSH(hw); + break; + default: + PMD_DRV_LOG(ERR, "PCTYPE[%u] not supported", info->pctype); + return -EINVAL; + } + + return 0; +} + +/* Get the symmetric hash enable configurations per port */ +static void +i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable) +{ + uint32_t reg = I40E_READ_REG(hw, I40E_PRTQF_CTL_0); + + *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0; +} + +/* Set the symmetric hash enable configurations per port */ +static void +i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable) +{ + uint32_t reg = I40E_READ_REG(hw, I40E_PRTQF_CTL_0); + + if (enable > 0) { + if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) { + PMD_DRV_LOG(INFO, "Symmetric hash has already " + "been enabled"); + return; + } + reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK; + } else { + if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) { + PMD_DRV_LOG(INFO, "Symmetric hash has already " + "been disabled"); + return; + } + reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK; + } + I40E_WRITE_REG(hw, I40E_PRTQF_CTL_0, reg); + I40E_WRITE_FLUSH(hw); +} + +/* Get filter swap configurations */ +static int +i40e_get_filter_swap(struct i40e_hw *hw, struct rte_eth_filter_swap_info *info) +{ + uint32_t reg; + + switch (info->pctype) { + case ETH_RSS_NONF_IPV4_UDP_SHIFT: + case ETH_RSS_NONF_IPV4_TCP_SHIFT: + case ETH_RSS_NONF_IPV4_SCTP_SHIFT: + case ETH_RSS_NONF_IPV4_OTHER_SHIFT: + case ETH_RSS_FRAG_IPV4_SHIFT: + case ETH_RSS_NONF_IPV6_UDP_SHIFT: + case ETH_RSS_NONF_IPV6_TCP_SHIFT: + case ETH_RSS_NONF_IPV6_SCTP_SHIFT: + case ETH_RSS_NONF_IPV6_OTHER_SHIFT: + case ETH_RSS_FRAG_IPV6_SHIFT: + case ETH_RSS_L2_PAYLOAD_SHIFT: + reg = I40E_READ_REG(hw, I40E_GLQF_SWAP(0, info->pctype)); + PMD_DRV_LOG(DEBUG, "Value read from I40E_GLQF_SWAP[0,%d]: " + "0x%x", info->pctype, reg); + + /** + * The offset and length read from register in word unit, + * which need to be converted in byte unit before being saved. + */ + info->off0_src0 = + (uint8_t)((reg & I40E_GLQF_SWAP_OFF0_SRC0_MASK) >> + I40E_GLQF_SWAP_OFF0_SRC0_SHIFT) << 1; + info->off0_src1 = + (uint8_t)((reg & I40E_GLQF_SWAP_OFF0_SRC1_MASK) >> + I40E_GLQF_SWAP_OFF0_SRC1_SHIFT) << 1; + info->len0 = (uint8_t)((reg & I40E_GLQF_SWAP_FLEN0_MASK) >> + I40E_GLQF_SWAP_FLEN0_SHIFT) << 1; + info->off1_src0 = + (uint8_t)((reg & I40E_GLQF_SWAP_OFF1_SRC0_MASK) >> + I40E_GLQF_SWAP_OFF1_SRC0_SHIFT) << 1; + info->off1_src1 = + (uint8_t)((reg & I40E_GLQF_SWAP_OFF1_SRC1_MASK) >> + I40E_GLQF_SWAP_OFF1_SRC1_SHIFT) << 1; + info->len1 = (uint8_t)((reg & I40E_GLQF_SWAP_FLEN1_MASK) >> + I40E_GLQF_SWAP_FLEN1_SHIFT) << 1; + break; + default: + PMD_DRV_LOG(ERR, "PCTYPE[%u] not supported", info->pctype); + return -EINVAL; + } + + return 0; +} + +/* Set filter swap configurations */ +static int +i40e_set_filter_swap(struct i40e_hw *hw, + const struct rte_eth_filter_swap_info *info) +{ +#define I40E_FIELD_LEN_MAX 0x1f +#define I40E_FIELD_OFFSET_MAX 0x7f + uint32_t reg; + + switch (info->pctype) { + case ETH_RSS_NONF_IPV4_UDP_SHIFT: + case ETH_RSS_NONF_IPV4_TCP_SHIFT: + case ETH_RSS_NONF_IPV4_SCTP_SHIFT: + case ETH_RSS_NONF_IPV4_OTHER_SHIFT: + case ETH_RSS_FRAG_IPV4_SHIFT: + case ETH_RSS_NONF_IPV6_UDP_SHIFT: + case ETH_RSS_NONF_IPV6_TCP_SHIFT: + case ETH_RSS_NONF_IPV6_SCTP_SHIFT: + case ETH_RSS_NONF_IPV6_OTHER_SHIFT: + case ETH_RSS_FRAG_IPV6_SHIFT: + case ETH_RSS_L2_PAYLOAD_SHIFT: + if (info->off0_src0 > I40E_FIELD_OFFSET_MAX) { + PMD_DRV_LOG(ERR, "off0_src0 (0x%x) exceeds the " + "maximum of 0x%x", info->off0_src0, + I40E_FIELD_OFFSET_MAX); + return I40E_ERR_PARAM; + } else if (info->off0_src1 > I40E_FIELD_OFFSET_MAX) { + PMD_DRV_LOG(ERR, "off0_src1 (0x%x) exceeds the " + "maximum of 0x%x", info->off0_src1, + I40E_FIELD_OFFSET_MAX); + return I40E_ERR_PARAM; + } else if (info->len0 > I40E_FIELD_LEN_MAX) { + PMD_DRV_LOG(ERR, "len0 (0x%x) exceeds the maximum " + "of 0x%x", info->len0, I40E_FIELD_LEN_MAX); + return I40E_ERR_PARAM; + } else if (info->off1_src0 > I40E_FIELD_OFFSET_MAX) { + PMD_DRV_LOG(ERR, "off1_src0 (0x%x) exceeds the " + "maximum of 0x%x", info->off1_src0, + I40E_FIELD_OFFSET_MAX); + return I40E_ERR_PARAM; + } else if (info->off1_src1 > I40E_FIELD_OFFSET_MAX) { + PMD_DRV_LOG(ERR, "off1_src1 (0x%x) exceeds the " + "maximum of 0x%x", info->off1_src1, + I40E_FIELD_OFFSET_MAX); + return I40E_ERR_PARAM; + } else if (info->len1 > I40E_FIELD_LEN_MAX) { + PMD_DRV_LOG(ERR, "len1 (0x%x) exceeds the maximum " + "of 0x%x", info->len1, I40E_FIELD_LEN_MAX); + return I40E_ERR_PARAM; + } + + /** + * The offset and length given in byte unit, which need to be + * converted in word unit before being written to the register, + * as hardware requires it in word unit. + */ + reg = (info->off0_src0 >> 1) << I40E_GLQF_SWAP_OFF0_SRC0_SHIFT; + reg |= (info->off0_src1 >> 1) << + I40E_GLQF_SWAP_OFF0_SRC1_SHIFT; + reg |= (info->len0 >> 1) << I40E_GLQF_SWAP_FLEN0_SHIFT; + reg |= (info->off1_src0 >> 1) << + I40E_GLQF_SWAP_OFF1_SRC0_SHIFT; + reg |= (info->off1_src1 >> 1) << + I40E_GLQF_SWAP_OFF1_SRC1_SHIFT; + reg |= (info->len1 >> 1) << I40E_GLQF_SWAP_FLEN1_SHIFT; + + PMD_DRV_LOG(DEBUG, "Value to be written to " + "I40E_GLQF_SWAP[0,%d]: 0x%x", info->pctype, reg); + I40E_WRITE_REG(hw, I40E_GLQF_SWAP(0, info->pctype), reg); + I40E_WRITE_FLUSH(hw); + break; + default: + PMD_DRV_LOG(ERR, "PCTYPE[%u] not supported", info->pctype); + return -EINVAL; + } + + return 0; +} + +/* Get hash function type */ +static void +i40e_get_hash_function(struct i40e_hw *hw, enum rte_eth_hash_function *hf) +{ + uint32_t reg = I40E_READ_REG(hw, I40E_GLQF_CTL); + + if (reg & I40E_GLQF_CTL_HTOEP_MASK) + *hf = RTE_ETH_HASH_FUNCTION_TOEPLITZ; + else + *hf = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR; + + PMD_DRV_LOG(INFO, "Hash function is %s", + (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR"); +} + +/* Set hash function type */ +static int +i40e_set_hash_function(struct i40e_hw *hw, enum rte_eth_hash_function hf) +{ + uint32_t reg = I40E_READ_REG(hw, I40E_GLQF_CTL); + + if (hf == RTE_ETH_HASH_FUNCTION_TOEPLITZ) { + if (reg & I40E_GLQF_CTL_HTOEP_MASK) { + PMD_DRV_LOG(DEBUG, "Hash function already set to " + "Toeplitz"); + return 0; + } + reg |= I40E_GLQF_CTL_HTOEP_MASK; + } else if (hf == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) { + if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) { + PMD_DRV_LOG(DEBUG, "Hash function already set to " + "Simple XOR"); + return 0; + } + reg &= ~I40E_GLQF_CTL_HTOEP_MASK; + } else { + PMD_DRV_LOG(ERR, "Unknown hash function type"); + return -EINVAL; + } + + PMD_DRV_LOG(INFO, "Hash function set to %s", + (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR"); + I40E_WRITE_REG(hw, I40E_GLQF_CTL, reg); + I40E_WRITE_FLUSH(hw); + + return 0; +} + +static int +i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info) +{ + int ret = 0; + + if (!hw || !info) { + PMD_DRV_LOG(ERR, "Invalid pointer"); + return -EFAULT; + } + + switch (info->info_type) { + case RTE_ETH_HASH_FILTER_INFO_TYPE_SYM_HASH_ENA_PER_PCTYPE: + ret = i40e_get_symmetric_hash_enable_per_pctype(hw, + &(info->info.sym_hash_ena)); + break; + case RTE_ETH_HASH_FILTER_INFO_TYPE_SYM_HASH_ENA_PER_PORT: + i40e_get_symmetric_hash_enable_per_port(hw, + &(info->info.enable)); + break; + case RTE_ETH_HASH_FILTER_INFO_TYPE_FILTER_SWAP: + ret = i40e_get_filter_swap(hw, &(info->info.filter_swap)); + break; + case RTE_ETH_HASH_FILTER_INFO_TYPE_HASH_FUNCTION: + i40e_get_hash_function(hw, &(info->info.hash_function)); + break; + default: + PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported", + info->info_type); + ret = -EINVAL; + break; + } + + return ret; +} + +static int +i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info) +{ + int ret = 0; + + if (!hw || !info) { + PMD_DRV_LOG(ERR, "Invalid pointer"); + return -EFAULT; + } + + switch (info->info_type) { + case RTE_ETH_HASH_FILTER_INFO_TYPE_SYM_HASH_ENA_PER_PCTYPE: + ret = i40e_set_symmetric_hash_enable_per_pctype(hw, + &(info->info.sym_hash_ena)); + break; + case RTE_ETH_HASH_FILTER_INFO_TYPE_SYM_HASH_ENA_PER_PORT: + i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable); + break; + case RTE_ETH_HASH_FILTER_INFO_TYPE_FILTER_SWAP: + ret = i40e_set_filter_swap(hw, &(info->info.filter_swap)); + break; + case RTE_ETH_HASH_FILTER_INFO_TYPE_HASH_FUNCTION: + ret = i40e_set_hash_function(hw, info->info.hash_function); + break; + default: + PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported", + info->info_type); + ret = -EINVAL; + break; + } + + return ret; +} + +/* Operations for hash function */ +static int +i40e_hash_filter_ctrl(struct rte_eth_dev *dev, + enum rte_filter_op filter_op, + void *arg) +{ + struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); + int ret = 0; + + switch (filter_op) { + case RTE_ETH_FILTER_NOP: + break; + case RTE_ETH_FILTER_GET: + ret = i40e_hash_filter_get(hw, + (struct rte_eth_hash_filter_info *)arg); + break; + case RTE_ETH_FILTER_SET: + ret = i40e_hash_filter_set(hw, + (struct rte_eth_hash_filter_info *)arg); + break; + default: + PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported", + filter_op); + ret = -ENOTSUP; + break; + } + + return ret; +} + static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev, enum rte_filter_type filter_type, @@ -4152,13 +4524,14 @@ i40e_dev_filter_ctrl(struct rte_eth_dev *dev, void *arg) { int ret = 0; - (void)filter_op; - (void)arg; if (dev == NULL) return -EINVAL; switch (filter_type) { + case RTE_ETH_FILTER_HASH: + ret = i40e_hash_filter_ctrl(dev, filter_op, arg); + break; default: PMD_DRV_LOG(WARNING, "Filter type (%d) not supported", filter_type);