From patchwork Thu Oct 16 10:07:21 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Chen, Jing D" X-Patchwork-Id: 827 Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [IPv6:::1]) by dpdk.org (Postfix) with ESMTP id E0EA97E85; Thu, 16 Oct 2014 12:00:04 +0200 (CEST) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by dpdk.org (Postfix) with ESMTP id 8ED3E7E78 for ; Thu, 16 Oct 2014 12:00:02 +0200 (CEST) Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga103.jf.intel.com with ESMTP; 16 Oct 2014 03:04:53 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.04,731,1406617200"; d="scan'208";a="619771460" Received: from shvmail01.sh.intel.com ([10.239.29.42]) by orsmga002.jf.intel.com with ESMTP; 16 Oct 2014 03:07:51 -0700 Received: from shecgisg003.sh.intel.com (shecgisg003.sh.intel.com [10.239.29.90]) by shvmail01.sh.intel.com with ESMTP id s9GA7mPP007041; Thu, 16 Oct 2014 18:07:48 +0800 Received: from shecgisg003.sh.intel.com (localhost [127.0.0.1]) by shecgisg003.sh.intel.com (8.13.6/8.13.6/SuSE Linux 0.8) with ESMTP id s9GA7jn3013448; Thu, 16 Oct 2014 18:07:48 +0800 Received: (from jingche2@localhost) by shecgisg003.sh.intel.com (8.13.6/8.13.6/Submit) id s9GA7jaY013444; Thu, 16 Oct 2014 18:07:45 +0800 From: "Chen Jing D(Mark)" To: dev@dpdk.org Date: Thu, 16 Oct 2014 18:07:21 +0800 Message-Id: <1413454046-13407-2-git-send-email-jing.d.chen@intel.com> X-Mailer: git-send-email 1.7.12.2 In-Reply-To: <1413454046-13407-1-git-send-email-jing.d.chen@intel.com> References: <1411478047-1251-2-git-send-email-jing.d.chen@intel.com> <1413454046-13407-1-git-send-email-jing.d.chen@intel.com> Subject: [dpdk-dev] [PATCH v2 1/6] ether: enhancement for VMDQ support X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: "Chen Jing D(Mark)" The change includes several parts: 1. Clear pool bitmap when trying to remove specific MAC. 2. Define RSS, DCB and VMDQ flags to combine rx_mq_mode. 3. Use 'struct' to replace 'union', which to expand the rx_adv_conf arguments to better support RSS, DCB and VMDQ. 4. Fix bug in rte_eth_dev_config_restore function, which will restore all MAC address to default pool. 5. Define additional 3 arguments for better VMDQ support. Signed-off-by: Chen Jing D(Mark) --- lib/librte_ether/rte_ethdev.c | 12 ++++++---- lib/librte_ether/rte_ethdev.h | 43 ++++++++++++++++++++++++++++++---------- 2 files changed, 39 insertions(+), 16 deletions(-) diff --git a/lib/librte_ether/rte_ethdev.c b/lib/librte_ether/rte_ethdev.c index fd1010a..86f4409 100644 --- a/lib/librte_ether/rte_ethdev.c +++ b/lib/librte_ether/rte_ethdev.c @@ -771,7 +771,8 @@ rte_eth_dev_config_restore(uint8_t port_id) continue; /* add address to the hardware */ - if (*dev->dev_ops->mac_addr_add) + if (*dev->dev_ops->mac_addr_add && + dev->data->mac_pool_sel[i] & (1ULL << pool)) (*dev->dev_ops->mac_addr_add)(dev, &addr, i, pool); else { PMD_DEBUG_TRACE("port %d: MAC address array not supported\n", @@ -1249,10 +1250,8 @@ rte_eth_dev_info_get(uint8_t port_id, struct rte_eth_dev_info *dev_info) } dev = &rte_eth_devices[port_id]; - /* Default device offload capabilities to zero */ - dev_info->rx_offload_capa = 0; - dev_info->tx_offload_capa = 0; - dev_info->if_index = 0; + /* Set all fields with zero */ + memset(dev_info, 0, sizeof(*dev_info)); FUNC_PTR_OR_RET(*dev->dev_ops->dev_infos_get); (*dev->dev_ops->dev_infos_get)(dev, dev_info); dev_info->pci_dev = dev->pci_dev; @@ -2022,6 +2021,9 @@ rte_eth_dev_mac_addr_remove(uint8_t port_id, struct ether_addr *addr) /* Update address in NIC data structure */ ether_addr_copy(&null_mac_addr, &dev->data->mac_addrs[index]); + /* reset pool bitmap */ + dev->data->mac_pool_sel[index] = 0; + return 0; } diff --git a/lib/librte_ether/rte_ethdev.h b/lib/librte_ether/rte_ethdev.h index 50df654..4c83aa5 100644 --- a/lib/librte_ether/rte_ethdev.h +++ b/lib/librte_ether/rte_ethdev.h @@ -252,20 +252,37 @@ struct rte_eth_thresh { }; /** + * Simple flags to indicate RX mq mode, which can be used independently or combined + * in enum rte_eth_rx_mq_mode definition. + */ +#define ETH_MQ_RX_RSS_FLAG 0x1 +#define ETH_MQ_RX_DCB_FLAG 0x2 +#define ETH_MQ_RX_VMDQ_FLAG 0x4 + +/** * A set of values to identify what method is to be used to route * packets to multiple queues. */ enum rte_eth_rx_mq_mode { - ETH_MQ_RX_NONE = 0, /**< None of DCB,RSS or VMDQ mode */ - - ETH_MQ_RX_RSS, /**< For RX side, only RSS is on */ - ETH_MQ_RX_DCB, /**< For RX side,only DCB is on. */ - ETH_MQ_RX_DCB_RSS, /**< Both DCB and RSS enable */ - - ETH_MQ_RX_VMDQ_ONLY, /**< Only VMDQ, no RSS nor DCB */ - ETH_MQ_RX_VMDQ_RSS, /**< RSS mode with VMDQ */ - ETH_MQ_RX_VMDQ_DCB, /**< Use VMDQ+DCB to route traffic to queues */ - ETH_MQ_RX_VMDQ_DCB_RSS, /**< Enable both VMDQ and DCB in VMDq */ + /**< None of DCB,RSS or VMDQ mode */ + ETH_MQ_RX_NONE = 0, + + /**< For RX side, only RSS is on */ + ETH_MQ_RX_RSS = ETH_MQ_RX_RSS_FLAG, + /**< For RX side,only DCB is on. */ + ETH_MQ_RX_DCB = ETH_MQ_RX_DCB_FLAG, + /**< Both DCB and RSS enable */ + ETH_MQ_RX_DCB_RSS = ETH_MQ_RX_RSS_FLAG | ETH_MQ_RX_DCB_FLAG, + + /**< Only VMDQ, no RSS nor DCB */ + ETH_MQ_RX_VMDQ_ONLY = ETH_MQ_RX_VMDQ_FLAG, + /**< RSS mode with VMDQ */ + ETH_MQ_RX_VMDQ_RSS = ETH_MQ_RX_RSS_FLAG | ETH_MQ_RX_VMDQ_FLAG, + /**< Use VMDQ+DCB to route traffic to queues */ + ETH_MQ_RX_VMDQ_DCB = ETH_MQ_RX_VMDQ_FLAG | ETH_MQ_RX_DCB_FLAG, + /**< Enable both VMDQ and DCB in VMDq */ + ETH_MQ_RX_VMDQ_DCB_RSS = ETH_MQ_RX_RSS_FLAG | ETH_MQ_RX_DCB_FLAG | + ETH_MQ_RX_VMDQ_FLAG, }; /** @@ -840,7 +857,7 @@ struct rte_eth_conf { Read the datasheet of given ethernet controller for details. The possible values of this field are defined in implementation of each driver. */ - union { + struct { struct rte_eth_rss_conf rss_conf; /**< Port RSS configuration */ struct rte_eth_vmdq_dcb_conf vmdq_dcb_conf; /**< Port vmdq+dcb configuration. */ @@ -906,6 +923,10 @@ struct rte_eth_dev_info { uint16_t max_vmdq_pools; /**< Maximum number of VMDq pools. */ uint32_t rx_offload_capa; /**< Device RX offload capabilities. */ uint32_t tx_offload_capa; /**< Device TX offload capabilities. */ + /** Specify the queue range belongs to VMDQ pools if VMDQ applicable. */ + uint16_t vmdq_queue_base; + uint16_t vmdq_queue_num; + uint16_t vmdq_pool_base; /**< First ID of VMDQ pools. */ }; struct rte_eth_dev;