[dpdk-dev,05/12] Add prefetch operation for IBM Power architecture
Commit Message
The prefetch operations implemented with assembly code in DPDK only
support x86. This patch add architecture specific prefetch operations
for IBM Power architecture.
Signed-off-by: Chao Zhu <bjzhuc@cn.ibm.com>
---
.../include/powerpc/arch/rte_prefetch_arch.h | 67 ++++++++++++++++++++
1 files changed, 67 insertions(+), 0 deletions(-)
create mode 100644 lib/librte_eal/common/include/powerpc/arch/rte_prefetch_arch.h
new file mode 100644
@@ -0,0 +1,67 @@
+/*
+ * BSD LICENSE
+ *
+ * Copyright (C) IBM Corporation 2014.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of IBM Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+#ifndef _RTE_PREFETCH_ARCH_H_
+#define _RTE_PREFETCH_ARCH_H_
+
+/**
+ * Prefetch a cache line into all cache levels.
+ * @param p
+ * Address to prefetch
+ */
+static inline void rte_arch_prefetch0(volatile void *p)
+{
+ asm volatile ("dcbt 0,%[p],1" : : [p] "r" (p));
+}
+
+/**
+ * Prefetch a cache line into all cache levels except the 0th cache level.
+ * @param p
+ * Address to prefetch
+ */
+static inline void rte_arch_prefetch1(volatile void *p)
+{
+ asm volatile ("dcbt 0,%[p],1" : : [p] "r" (p));
+}
+
+/**
+ * Prefetch a cache line into all cache levels except the 0th and 1th cache
+ * levels.
+ * @param p
+ * Address to prefetch
+ */
+static inline void rte_arch_prefetch2(volatile void *p)
+{
+ asm volatile ("dcbt 0,%[p],1" : : [p] "r" (p));
+}
+
+#endif /* _RTE_PREFETCH_ARCH_H_ */