From patchwork Fri Sep 26 09:36:18 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chao Zhu X-Patchwork-Id: 579 Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [IPv6:::1]) by dpdk.org (Postfix) with ESMTP id 0ED197E67; Fri, 26 Sep 2014 11:30:32 +0200 (CEST) Received: from e7.ny.us.ibm.com (e7.ny.us.ibm.com [32.97.182.137]) by dpdk.org (Postfix) with ESMTP id B1D9E7E2C for ; Fri, 26 Sep 2014 11:30:21 +0200 (CEST) Received: from /spool/local by e7.ny.us.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Fri, 26 Sep 2014 05:36:42 -0400 Received: from d01dlp01.pok.ibm.com (9.56.250.166) by e7.ny.us.ibm.com (192.168.1.107) with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted; Fri, 26 Sep 2014 05:36:40 -0400 Received: from b01cxnp22034.gho.pok.ibm.com (b01cxnp22034.gho.pok.ibm.com [9.57.198.24]) by d01dlp01.pok.ibm.com (Postfix) with ESMTP id E031C38C803D for ; Fri, 26 Sep 2014 05:36:39 -0400 (EDT) Received: from d01av05.pok.ibm.com (d01av05.pok.ibm.com [9.56.224.195]) by b01cxnp22034.gho.pok.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id s8Q9aV3J9306582 for ; Fri, 26 Sep 2014 09:36:39 GMT Received: from d01av05.pok.ibm.com (localhost [127.0.0.1]) by d01av05.pok.ibm.com (8.14.4/8.14.4/NCO v10.0 AVout) with ESMTP id s8Q9a7ir002930 for ; Fri, 26 Sep 2014 05:36:07 -0400 Received: from d01hub02.pok.ibm.com (d01hub02.pok.ibm.com [9.63.10.236]) by d01av05.pok.ibm.com (8.14.4/8.14.4/NCO v10.0 AVin) with ESMTP id s8Q9a7wH002655 for ; Fri, 26 Sep 2014 05:36:07 -0400 Received: from localhost.localdomain ([9.186.57.14]) by rescrl1.research.ibm.com (IBM Domino Release 9.0.1) with ESMTP id 2014092617352131-312550 ; Fri, 26 Sep 2014 17:35:21 +0800 From: Chao Zhu To: dev@dpdk.org Date: Fri, 26 Sep 2014 05:36:18 -0400 Message-Id: <1411724186-8036-5-git-send-email-bjzhuc@cn.ibm.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1411724186-8036-1-git-send-email-bjzhuc@cn.ibm.com> References: <1411724186-8036-1-git-send-email-bjzhuc@cn.ibm.com> X-MIMETrack: Itemize by SMTP Server on rescrl1/Research/Affiliated/IBM(Release 9.0.1|October 14, 2013) at 2014/09/26 17:35:21, Serialize by Router on D01HUB02/01/H/IBM(Release 8.5.3FP2 ZX853FP2HF5|February, 2013) at 09/26/2014 05:36:06, Serialize complete at 09/26/2014 05:36:06 X-TM-AS-MML: disable X-Content-Scanned: Fidelis XPS MAILER x-cbid: 14092609-5806-0000-0000-00000098F229 Subject: [dpdk-dev] [PATCH 04/12] Add CPU cycle operations for IBM Power architecture X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" IBM Power architecture doesn't have TSC register to get CPU cycles. This patch implements the time base register read instead of TSC register of x86 on IBM Power architecture. Signed-off-by: Chao Zhu --- .../common/include/powerpc/arch/rte_cycles_arch.h | 67 ++++++++++++++++++++ 1 files changed, 67 insertions(+), 0 deletions(-) create mode 100644 lib/librte_eal/common/include/powerpc/arch/rte_cycles_arch.h diff --git a/lib/librte_eal/common/include/powerpc/arch/rte_cycles_arch.h b/lib/librte_eal/common/include/powerpc/arch/rte_cycles_arch.h new file mode 100644 index 0000000..faae7a6 --- /dev/null +++ b/lib/librte_eal/common/include/powerpc/arch/rte_cycles_arch.h @@ -0,0 +1,67 @@ +/* + * BSD LICENSE + * + * Copyright (C) IBM Corporation 2014. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of IBM Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + +#ifndef _RTE_CYCLES_ARCH_H_ +#define _RTE_CYCLES_ARCH_H_ + +#include + +/** + * Read the time base register. + * + * @return + * The time base for this lcore. + */ +static inline uint64_t +rte_arch_rdtsc(void) +{ + union { + uint64_t tsc_64; + struct { + uint32_t hi_32; + uint32_t lo_32; + }; + } tsc; + uint32_t tmp; + asm volatile( + "0:\n" + "mftbu %[hi32]\n" + "mftb %[lo32]\n" + "mftbu %[tmp]\n" + "cmpw %[tmp],%[hi32]\n" + "bne 0b\n" + : [hi32] "=r"(tsc.hi_32), [lo32] "=r"(tsc.lo_32), [tmp] "=r"(tmp) + ); + return tsc.tsc_64; +} +#endif /* _RTE_CYCLES_ARCH_H_ */ +