diff mbox

[dpdk-dev,10/12] Add cache size define for IBM Power Architecture

Message ID 1411724186-8036-11-git-send-email-bjzhuc@cn.ibm.com (mailing list archive)
State Superseded, archived
Headers

Commit Message

Chao Zhu Sept. 26, 2014, 9:36 a.m. UTC 
IBM Power architecture has different cache line size (128 bytes) than
x86 (64 bytes). This patch defines CACHE_LINE_SIZE to 128 bytes to
override the default value 64 bytes to support IBM Power Architecture.

Signed-off-by: Chao Zhu <bjzhuc@cn.ibm.com>
---
 app/test/test_malloc.c      |    8 ++++----
 app/test/test_mbuf.c        |    2 +-
 mk/arch/powerpc/rte.vars.mk |    2 +-
 3 files changed, 6 insertions(+), 6 deletions(-)

Comments

Hemant Agrawal Sept. 29, 2014, 6:21 a.m. UTC | #1 
> --- a/mk/arch/powerpc/rte.vars.mk
> +++ b/mk/arch/powerpc/rte.vars.mk
> @@ -32,7 +32,7 @@
>  ARCH  ?= powerpc
>  CROSS ?=
> 
> -CPU_CFLAGS  ?= -m64
> +CPU_CFLAGS  ?= -m64 -DCACHE_LINE_SIZE=128

 [hemant]  Instead of hardcoding the CACHE_LINE_SIZE,  can you drive the CACHE_LINE_SIZE from config file.  Other powerpc processor have it as 64.


>  CPU_LDFLAGS ?=
>  CPU_ASFLAGS ?= -felf64
> 
> --
> 1.7.1
Chao Zhu Sept. 29, 2014, 6:40 a.m. UTC | #2 
Hi,Hemant, 

Actually, the set of patches is only for IBM Power7/8 which has difference 
cache line size. Of cause, a better way may be detecting the cache line 
size at runtime not from configuration files... May be we can submit this 
kind of patch later. 

Best Regards!
------------------------------
Chao Zhu (祝超)
Research Staff Member
Cloud Infrastructure and Technology Group
IBM China Research Lab
Building 19 Zhongguancun Software Park
8 Dongbeiwang West Road, Haidian District,
Beijing, PRC. 100193
Tel: +86-10-58748711
Email: bjzhuc@cn.ibm.com




From:   "Hemant@freescale.com" <Hemant@freescale.com>

To:     Chao CH Zhu/China/IBM@IBMCN, "dev@dpdk.org" <dev@dpdk.org>
Date:   2014/09/29 14:20
Subject:        RE: [dpdk-dev] [PATCH 10/12] Add cache size define for IBM 
Power   Architecture



> --- a/mk/arch/powerpc/rte.vars.mk

> +++ b/mk/arch/powerpc/rte.vars.mk

> @@ -32,7 +32,7 @@

>  ARCH  ?= powerpc

>  CROSS ?=

> 

> -CPU_CFLAGS  ?= -m64

> +CPU_CFLAGS  ?= -m64 -DCACHE_LINE_SIZE=128


 [hemant]  Instead of hardcoding the CACHE_LINE_SIZE,  can you drive the 
CACHE_LINE_SIZE from config file.  Other powerpc processor have it as 64.


>  CPU_LDFLAGS ?=

>  CPU_ASFLAGS ?= -felf64

> 

> --

> 1.7.1
diff mbox

Patch

diff --git a/app/test/test_malloc.c b/app/test/test_malloc.c
index ee34ca3..63e6b32 100644
--- a/app/test/test_malloc.c
+++ b/app/test/test_malloc.c
@@ -300,9 +300,9 @@  test_big_alloc(void)
 	size_t size =rte_str_to_size(MALLOC_MEMZONE_SIZE)*2;
 	int align = 0;
 #ifndef RTE_LIBRTE_MALLOC_DEBUG
-	int overhead = 64 + 64;
+	int overhead = CACHE_LINE_SIZE + CACHE_LINE_SIZE;
 #else
-	int overhead = 64 + 64 + 64;
+	int overhead = CACHE_LINE_SIZE + CACHE_LINE_SIZE + CACHE_LINE_SIZE;
 #endif
 
 	rte_malloc_get_socket_stats(socket, &pre_stats);
@@ -356,9 +356,9 @@  test_multi_alloc_statistics(void)
 #ifndef RTE_LIBRTE_MALLOC_DEBUG
 	int trailer_size = 0;
 #else
-	int trailer_size = 64;
+	int trailer_size = CACHE_LINE_SIZE;
 #endif
-	int overhead = 64 + trailer_size;
+	int overhead = CACHE_LINE_SIZE + trailer_size;
 
 	rte_malloc_get_socket_stats(socket, &pre_stats);
 
diff --git a/app/test/test_mbuf.c b/app/test/test_mbuf.c
index 21024e7..03da329 100644
--- a/app/test/test_mbuf.c
+++ b/app/test/test_mbuf.c
@@ -832,7 +832,7 @@  test_failing_mbuf_sanity_check(void)
 static int
 test_mbuf(void)
 {
-	RTE_BUILD_BUG_ON(sizeof(struct rte_mbuf) != 64);
+	RTE_BUILD_BUG_ON(sizeof(struct rte_mbuf) != CACHE_LINE_SIZE);
 
 	/* create pktmbuf pool if it does not exist */
 	if (pktmbuf_pool == NULL) {
diff --git a/mk/arch/powerpc/rte.vars.mk b/mk/arch/powerpc/rte.vars.mk
index 363fcd1..dfdeaea 100644
--- a/mk/arch/powerpc/rte.vars.mk
+++ b/mk/arch/powerpc/rte.vars.mk
@@ -32,7 +32,7 @@ 
 ARCH  ?= powerpc
 CROSS ?=
 
-CPU_CFLAGS  ?= -m64
+CPU_CFLAGS  ?= -m64 -DCACHE_LINE_SIZE=128
 CPU_LDFLAGS ?=
 CPU_ASFLAGS ?= -felf64