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[dpdk-dev,v3,03/20] i40e: initialize flexible payload setting

Message ID 1411711418-12881-4-git-send-email-jingjing.wu@intel.com (mailing list archive)
State Superseded, archived
Headers show

Commit Message

Jingjing Wu Sept. 26, 2014, 6:03 a.m. UTC
set flexible payload related registers to default value at initialization time.

Signed-off-by: Jingjing Wu <jingjing.wu@intel.com>
Acked-by: Chen Jing D(Mark) <jing.d.chen@intel.com>
Acked-by: Helin Zhang <helin.zhang@intel.com>
---
 lib/librte_pmd_i40e/i40e_ethdev.c | 33 ++++++++++++++++++++++++++
 lib/librte_pmd_i40e/i40e_fdir.c   | 49 +++++++++++++++++++++++++++++++++++++++
 2 files changed, 82 insertions(+)
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Patch

diff --git a/lib/librte_pmd_i40e/i40e_ethdev.c b/lib/librte_pmd_i40e/i40e_ethdev.c
index da131a8..a3f25e6 100644
--- a/lib/librte_pmd_i40e/i40e_ethdev.c
+++ b/lib/librte_pmd_i40e/i40e_ethdev.c
@@ -336,6 +336,32 @@  static struct rte_driver rte_i40e_driver = {
 
 PMD_REGISTER_DRIVER(rte_i40e_driver);
 
+/*
+ * Initialize registers for flexible payload, which should be set by NVM.
+ * This should be removed from code once is fixed in NVM.
+ */
+static inline void i40e_flex_payload_reg_init(struct i40e_hw *hw)
+{
+	/* GLQF_ORT Registers */
+	I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
+	I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
+	I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
+	I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);
+	I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
+	I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
+	I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
+	I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
+	I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
+	I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
+
+	/* GLQF_PIT Registers */
+	I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
+	I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
+
+	/* GL_PRS_FVBM Registers */
+	I40E_WRITE_REG(hw, I40E_GL_PRS_FVBM(1), 0x8000035B);
+}
+
 static int
 eth_i40e_dev_init(__rte_unused struct eth_driver *eth_drv,
                   struct rte_eth_dev *dev)
@@ -399,6 +425,13 @@  eth_i40e_dev_init(__rte_unused struct eth_driver *eth_drv,
 		return ret;
 	}
 
+	/*
+	 * To work around the NVM issue,initialize registers
+	 * for flexible payload by software.
+	 * It should be removed once issues are fixed in NVM.
+	 */
+	i40e_flex_payload_reg_init(hw);
+
 	/* Initialize the parameters for adminq */
 	i40e_init_adminq_parameter(hw);
 	ret = i40e_init_adminq(hw);
diff --git a/lib/librte_pmd_i40e/i40e_fdir.c b/lib/librte_pmd_i40e/i40e_fdir.c
index 3d8faa0..a3e6bd7 100644
--- a/lib/librte_pmd_i40e/i40e_fdir.c
+++ b/lib/librte_pmd_i40e/i40e_fdir.c
@@ -109,6 +109,53 @@  i40e_fdir_rx_queue_init(struct i40e_rx_queue *rxq)
 }
 
 /*
+ * Initialize the configuration about bytes stream extracted as flexible payload
+ * and mask setting
+ */
+static inline void
+i40e_init_flx_pld(struct i40e_pf *pf)
+{
+	uint8_t pctype;;
+	struct i40e_hw *hw = I40E_PF_TO_HW(pf);
+
+	/*
+	 * Define the bytes stream extracted as flexible payload in
+	 * field vector. By default, select 8 words from the beginning
+	 * of payload as flexible payload.
+	 */
+	memset(pf->fdir.flex_set, 0, sizeof(pf->fdir.flex_set));
+
+	/* initialize the flexible payload for L2 payload*/
+	pf->fdir.flex_set[0][0].offset = 0;
+	pf->fdir.flex_set[0][0].size = 8;
+	I40E_WRITE_REG(hw, I40E_PRTQF_FLX_PIT(0), 0x0000C900);
+	I40E_WRITE_REG(hw, I40E_PRTQF_FLX_PIT(1), 0x0000FC29);/*non-used*/
+	I40E_WRITE_REG(hw, I40E_PRTQF_FLX_PIT(2), 0x0000FC2A);/*non-used*/
+
+	/* initialize the flexible payload for L3 payload*/
+	pf->fdir.flex_set[1][0].offset = 0;
+	pf->fdir.flex_set[1][0].size = 8;
+	I40E_WRITE_REG(hw, I40E_PRTQF_FLX_PIT(3), 0x0000C900);
+	I40E_WRITE_REG(hw, I40E_PRTQF_FLX_PIT(4), 0x0000FC29);/*non-used*/
+	I40E_WRITE_REG(hw, I40E_PRTQF_FLX_PIT(5), 0x0000FC2A);/*non-used*/
+
+	/* initialize the flexible payload for L4 payload*/
+	pf->fdir.flex_set[2][0].offset = 0;
+	pf->fdir.flex_set[2][0].size = 8;
+	I40E_WRITE_REG(hw, I40E_PRTQF_FLX_PIT(6), 0x0000C900);
+	I40E_WRITE_REG(hw, I40E_PRTQF_FLX_PIT(7), 0x0000FC29);/*non-used*/
+	I40E_WRITE_REG(hw, I40E_PRTQF_FLX_PIT(8), 0x0000FC2A);/*non-used*/
+
+	/* initialize the masks */
+	for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
+	     pctype <= I40E_FILTER_PCTYPE_FRAG_IPV6; pctype++) {
+		I40E_WRITE_REG(hw, I40E_PRTQF_FD_FLXINSET(pctype), 0);
+		I40E_WRITE_REG(hw, I40E_PRTQF_FD_MSK(pctype, 0), 0);
+		I40E_WRITE_REG(hw, I40E_PRTQF_FD_MSK(pctype, 1), 0);
+	}
+}
+
+/*
  * i40e_fdir_setup - reserve and initialize the Flow Director resources
  * @pf: board private structure
  */
@@ -182,6 +229,8 @@  i40e_fdir_setup(struct i40e_pf *pf)
 		goto fail_mem;
 	}
 
+	i40e_init_flx_pld(pf);
+
 	/* reserve memory for the fdir programming packet */
 	snprintf(z_name, sizeof(z_name), "%s_%s_%d",
 			eth_dev->driver->pci_drv.name,