From patchwork Thu Sep 25 08:40:20 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Zhang, Helin" X-Patchwork-Id: 502 Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [IPv6:::1]) by dpdk.org (Postfix) with ESMTP id 0D5A3B3DE; Thu, 25 Sep 2014 10:34:56 +0200 (CEST) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by dpdk.org (Postfix) with ESMTP id B04D8B3DE for ; Thu, 25 Sep 2014 10:34:54 +0200 (CEST) Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga101.fm.intel.com with ESMTP; 25 Sep 2014 01:40:48 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.04,595,1406617200"; d="scan'208";a="605124862" Received: from shvmail01.sh.intel.com ([10.239.29.42]) by fmsmga002.fm.intel.com with ESMTP; 25 Sep 2014 01:40:47 -0700 Received: from shecgisg004.sh.intel.com (shecgisg004.sh.intel.com [10.239.29.89]) by shvmail01.sh.intel.com with ESMTP id s8P8eiwt002315; Thu, 25 Sep 2014 16:40:44 +0800 Received: from shecgisg004.sh.intel.com (localhost [127.0.0.1]) by shecgisg004.sh.intel.com (8.13.6/8.13.6/SuSE Linux 0.8) with ESMTP id s8P8egl8000823; Thu, 25 Sep 2014 16:40:44 +0800 Received: (from hzhan75@localhost) by shecgisg004.sh.intel.com (8.13.6/8.13.6/Submit) id s8P8egER000819; Thu, 25 Sep 2014 16:40:42 +0800 From: Helin Zhang To: dev@dpdk.org Date: Thu, 25 Sep 2014 16:40:20 +0800 Message-Id: <1411634427-746-7-git-send-email-helin.zhang@intel.com> X-Mailer: git-send-email 1.7.4.1 In-Reply-To: <1411634427-746-1-git-send-email-helin.zhang@intel.com> References: <1411634427-746-1-git-send-email-helin.zhang@intel.com> Subject: [dpdk-dev] [PATCH v2 06/13] igb: rework of updating/querying reta X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" As ethdev has been changed to support multiple sizes of reta, updating/querying reta should be reworked to support that change. v2 changes: * Put rework of updating/querying igb reta to a single patch. Signed-off-by: Helin Zhang Reviewed-by: Jijiang Liu Reviewed-by: Cunming Liang Reviewed-by: Jingjing Wu --- lib/librte_pmd_e1000/igb_ethdev.c | 109 ++++++++++++++++++++------------------ 1 file changed, 56 insertions(+), 53 deletions(-) diff --git a/lib/librte_pmd_e1000/igb_ethdev.c b/lib/librte_pmd_e1000/igb_ethdev.c index 6646029..2fd30e4 100644 --- a/lib/librte_pmd_e1000/igb_ethdev.c +++ b/lib/librte_pmd_e1000/igb_ethdev.c @@ -126,10 +126,11 @@ static int igbvf_vlan_filter_set(struct rte_eth_dev *dev, static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on); static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on); static int eth_igb_rss_reta_update(struct rte_eth_dev *dev, - struct rte_eth_rss_reta *reta_conf); + struct rte_eth_rss_reta_entry64 *reta_conf, + uint16_t reta_size); static int eth_igb_rss_reta_query(struct rte_eth_dev *dev, - struct rte_eth_rss_reta *reta_conf); - + struct rte_eth_rss_reta_entry64 *reta_conf, + uint16_t reta_size); static int eth_igb_add_syn_filter(struct rte_eth_dev *dev, struct rte_syn_filter *filter, uint16_t rx_queue); static int eth_igb_remove_syn_filter(struct rte_eth_dev *dev); @@ -2250,38 +2251,39 @@ igbvf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on) static int eth_igb_rss_reta_update(struct rte_eth_dev *dev, - struct rte_eth_rss_reta *reta_conf) + struct rte_eth_rss_reta_entry64 *reta_conf, + uint16_t reta_size) { - uint8_t i,j,mask; - uint32_t reta; - struct e1000_hw *hw = - E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); + uint8_t i, j, mask; + uint32_t reta, r; + uint16_t idx, shift; + struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); - /* - * Update Redirection Table RETA[n],n=0...31,The redirection table has - * 128-entries in 32 registers - */ - for(i = 0; i < ETH_RSS_RETA_NUM_ENTRIES; i += 4) { - if (i < ETH_RSS_RETA_NUM_ENTRIES/2) - mask = (uint8_t)((reta_conf->mask_lo >> i) & 0xF); + if (reta_size != ETH_RSS_RETA_SIZE_128) { + PMD_DRV_LOG(ERR, "The size of hash lookup table configured " + "(%d) doesn't match the number hardware can supported " + "(%d)\n", reta_size, ETH_RSS_RETA_SIZE_128); + return -EINVAL; + } + + for (i = 0; i < reta_size; i += 4) { + idx = i / RTE_BIT_WIDTH_64; + shift = i % RTE_BIT_WIDTH_64; + mask = (uint8_t)((reta_conf[idx].mask >> shift) & 0xf); + if (!mask) + continue; + if (mask == 0xf) + r = 0; else - mask = (uint8_t)((reta_conf->mask_hi >> - (i - ETH_RSS_RETA_NUM_ENTRIES/2)) & 0xF); - if (mask != 0) { - reta = 0; - /* If all 4 entries were set,don't need read RETA register */ - if (mask != 0xF) - reta = E1000_READ_REG(hw,E1000_RETA(i >> 2)); - - for (j = 0; j < 4; j++) { - if (mask & (0x1 << j)) { - if (mask != 0xF) - reta &= ~(0xFF << 8 * j); - reta |= reta_conf->reta[i + j] << 8 * j; - } - } - E1000_WRITE_REG(hw, E1000_RETA(i >> 2),reta); + r = E1000_READ_REG(hw, E1000_RETA(i >> 2)); + for (j = 0, reta = 0; j < 4; j++) { + if (mask & (0x1 << j)) + reta |= reta_conf[idx].reta[shift + j] << + (CHAR_BIT * j); + else + reta |= r & (0xff << (CHAR_BIT * j)); } + E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta); } return 0; @@ -2289,31 +2291,32 @@ eth_igb_rss_reta_update(struct rte_eth_dev *dev, static int eth_igb_rss_reta_query(struct rte_eth_dev *dev, - struct rte_eth_rss_reta *reta_conf) + struct rte_eth_rss_reta_entry64 *reta_conf, + uint16_t reta_size) { - uint8_t i,j,mask; + uint8_t i, j, mask; uint32_t reta; - struct e1000_hw *hw = - E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); + uint16_t idx, shift; + struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); - /* - * Read Redirection Table RETA[n],n=0...31,The redirection table has - * 128-entries in 32 registers - */ - for(i = 0; i < ETH_RSS_RETA_NUM_ENTRIES; i += 4) { - if (i < ETH_RSS_RETA_NUM_ENTRIES/2) - mask = (uint8_t)((reta_conf->mask_lo >> i) & 0xF); - else - mask = (uint8_t)((reta_conf->mask_hi >> - (i - ETH_RSS_RETA_NUM_ENTRIES/2)) & 0xF); - - if (mask != 0) { - reta = E1000_READ_REG(hw,E1000_RETA(i >> 2)); - for (j = 0; j < 4; j++) { - if (mask & (0x1 << j)) - reta_conf->reta[i + j] = - (uint8_t)((reta >> 8 * j) & 0xFF); - } + if (reta_size != ETH_RSS_RETA_SIZE_128) { + PMD_DRV_LOG(ERR, "The size of hash lookup table configured " + "(%d) doesn't match the number hardware can supported " + "(%d)\n", reta_size, ETH_RSS_RETA_SIZE_128); + return -EINVAL; + } + + for (i = 0; i < reta_size; i += 4) { + idx = i / RTE_BIT_WIDTH_64; + shift = i % RTE_BIT_WIDTH_64; + mask = (uint8_t)((reta_conf[idx].mask >> shift) & 0xf); + if (!mask) + continue; + reta = E1000_READ_REG(hw, E1000_RETA(i >> 2)); + for (j = 0; j < 4; j++) { + if (mask & (0x1 << j)) + reta_conf[idx].reta[shift + j] = + ((reta >> (CHAR_BIT * j)) & 0xff); } }