From patchwork Tue Sep 9 07:21:32 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Zhang, Helin" X-Patchwork-Id: 322 Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [IPv6:::1]) by dpdk.org (Postfix) with ESMTP id 28EFEB3B3; Tue, 9 Sep 2014 09:17:13 +0200 (CEST) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by dpdk.org (Postfix) with ESMTP id 3DE52B3B9 for ; Tue, 9 Sep 2014 09:17:09 +0200 (CEST) Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga102.jf.intel.com with ESMTP; 09 Sep 2014 00:16:04 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.04,491,1406617200"; d="scan'208";a="570392074" Received: from shvmail01.sh.intel.com ([10.239.29.42]) by orsmga001.jf.intel.com with ESMTP; 09 Sep 2014 00:22:08 -0700 Received: from shecgisg004.sh.intel.com (shecgisg004.sh.intel.com [10.239.29.89]) by shvmail01.sh.intel.com with ESMTP id s897M7SL008875; Tue, 9 Sep 2014 15:22:07 +0800 Received: from shecgisg004.sh.intel.com (localhost [127.0.0.1]) by shecgisg004.sh.intel.com (8.13.6/8.13.6/SuSE Linux 0.8) with ESMTP id s897M4qd004481; Tue, 9 Sep 2014 15:22:06 +0800 Received: (from hzhan75@localhost) by shecgisg004.sh.intel.com (8.13.6/8.13.6/Submit) id s897M4ek004477; Tue, 9 Sep 2014 15:22:04 +0800 From: Helin Zhang To: dev@dpdk.org Date: Tue, 9 Sep 2014 15:21:32 +0800 Message-Id: <1410247299-4365-9-git-send-email-helin.zhang@intel.com> X-Mailer: git-send-email 1.7.4.1 In-Reply-To: <1410247299-4365-1-git-send-email-helin.zhang@intel.com> References: <1410247299-4365-1-git-send-email-helin.zhang@intel.com> Subject: [dpdk-dev] [PATCH 08/15] i40e: remove code which is for software validation only X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" The code wrapped in '#ifdef I40E_DCB_SW' is currently for software validation only, it should be removed at all. Signed-off-by: Helin Zhang Reviewed-by: Chen Jing --- lib/librte_pmd_i40e/i40e/i40e_common.c | 27 -- lib/librte_pmd_i40e/i40e/i40e_dcb.c | 625 ------------------------------ lib/librte_pmd_i40e/i40e/i40e_dcb.h | 103 ----- lib/librte_pmd_i40e/i40e/i40e_prototype.h | 6 - lib/librte_pmd_i40e/i40e/i40e_type.h | 40 -- 5 files changed, 801 deletions(-) diff --git a/lib/librte_pmd_i40e/i40e/i40e_common.c b/lib/librte_pmd_i40e/i40e/i40e_common.c index 4254aad..4f11542 100644 --- a/lib/librte_pmd_i40e/i40e/i40e_common.c +++ b/lib/librte_pmd_i40e/i40e/i40e_common.c @@ -4575,33 +4575,6 @@ enum i40e_status_code i40e_aq_set_oem_mode(struct i40e_hw *hw, return status; } -#ifdef I40E_DCB_SW - -/** - * i40e_aq_suspend_port_tx - * @hw: pointer to the hardware structure - * @seid: port seid - * @cmd_details: pointer to command details structure or NULL - * - * Suspend port's Tx traffic - **/ -enum i40e_status_code i40e_aq_suspend_port_tx(struct i40e_hw *hw, u16 seid, - struct i40e_asq_cmd_details *cmd_details) -{ - struct i40e_aq_desc desc; - enum i40e_status_code status; - struct i40e_aqc_tx_sched_ind *cmd = - (struct i40e_aqc_tx_sched_ind *)&desc.params.raw; - - i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_suspend_port_tx); - - cmd->vsi_seid = CPU_TO_LE16(seid); - - status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); - - return status; -} -#endif /* I40E_DCB_SW */ /** * i40e_aq_resume_port_tx diff --git a/lib/librte_pmd_i40e/i40e/i40e_dcb.c b/lib/librte_pmd_i40e/i40e/i40e_dcb.c index 435cf80..d067028 100644 --- a/lib/librte_pmd_i40e/i40e/i40e_dcb.c +++ b/lib/librte_pmd_i40e/i40e/i40e_dcb.c @@ -477,628 +477,3 @@ enum i40e_status_code i40e_init_dcb(struct i40e_hw *hw) return ret; } -#ifdef I40E_DCB_SW - -/** - * i40e_dcbx_event_handler - * @hw: pointer to the hw struct - * @e: event data to be processed (LLDPDU) - * - * Process LLDP MIB Change event from the Firmware - **/ -enum i40e_status_code i40e_process_lldp_event(struct i40e_hw *hw, - struct i40e_arq_event_info *e) -{ - enum i40e_status_code ret = I40E_SUCCESS; - UNREFERENCED_2PARAMETER(hw, e); - - return ret; -} - -/** - * i40e_dcb_hw_rx_fifo_config - * @hw: pointer to the hw struct - * @ets_mode: Strict Priority or Round Robin mode - * @non_ets_mode: Strict Priority or Round Robin - * @max_exponent: Exponent to calculate max refill credits - * @lltc_map: Low latency TC bitmap - * - * Configure HW Rx FIFO as part of DCB configuration. - **/ -void i40e_dcb_hw_rx_fifo_config(struct i40e_hw *hw, - enum i40e_dcb_arbiter_mode ets_mode, - enum i40e_dcb_arbiter_mode non_ets_mode, - u32 max_exponent, - u8 lltc_map) -{ - u32 reg = 0; - - reg = rd32(hw, I40E_PRTDCB_RETSC); - - reg &= ~I40E_PRTDCB_RETSC_ETS_MODE_MASK; - reg |= ((u32)ets_mode << I40E_PRTDCB_RETSC_ETS_MODE_SHIFT) & - I40E_PRTDCB_RETSC_ETS_MODE_MASK; - - reg &= ~I40E_PRTDCB_RETSC_NON_ETS_MODE_MASK; - reg |= ((u32)non_ets_mode << I40E_PRTDCB_RETSC_NON_ETS_MODE_SHIFT) & - I40E_PRTDCB_RETSC_NON_ETS_MODE_MASK; - - reg &= ~I40E_PRTDCB_RETSC_ETS_MAX_EXP_MASK; - reg |= (max_exponent << I40E_PRTDCB_RETSC_ETS_MAX_EXP_SHIFT) & - I40E_PRTDCB_RETSC_ETS_MAX_EXP_MASK; - - reg &= ~I40E_PRTDCB_RETSC_LLTC_MASK; - reg |= (lltc_map << I40E_PRTDCB_RETSC_LLTC_SHIFT) & - I40E_PRTDCB_RETSC_LLTC_MASK; - wr32(hw, I40E_PRTDCB_RETSC, reg); -} - -/** - * i40e_dcb_hw_rx_cmd_monitor_config - * @hw: pointer to the hw struct - * @num_tc: Total number of traffic class - * @num_ports: Total number of ports on device - * - * Configure HW Rx command monitor as part of DCB configuration. - **/ -void i40e_dcb_hw_rx_cmd_monitor_config(struct i40e_hw *hw, - u8 num_tc, u8 num_ports) -{ - u32 threshold = 0; - u32 fifo_size = 0; - u32 reg = 0; - - /* Set the threshold and fifo_size based on number of ports */ - switch (num_ports) { - case 1: - threshold = 0xF; - fifo_size = 0x10; - break; - case 2: - if (num_tc > 4) { - threshold = 0xC; - fifo_size = 0x8; - } else { - threshold = 0xF; - fifo_size = 0x10; - } - break; - case 4: - if (num_tc > 4) { - threshold = 0x6; - fifo_size = 0x4; - } else { - threshold = 0x9; - fifo_size = 0x8; - } - break; - } - - - reg = rd32(hw, I40E_PRTDCB_RPPMC); - reg &= ~I40E_PRTDCB_RPPMC_RX_FIFO_SIZE_MASK; - reg |= (fifo_size << I40E_PRTDCB_RPPMC_RX_FIFO_SIZE_SHIFT) & - I40E_PRTDCB_RPPMC_RX_FIFO_SIZE_MASK; - wr32(hw, I40E_PRTDCB_RPPMC, reg); -} - -/** - * i40e_dcb_hw_pfc_config - * @hw: pointer to the hw struct - * @pfc_en: Bitmap of PFC enabled priorities - * @prio_tc: priority to tc assignment indexed by priority - * - * Configure HW Priority Flow Controller as part of DCB configuration. - **/ -void i40e_dcb_hw_pfc_config(struct i40e_hw *hw, - u8 pfc_en, u8 *prio_tc) -{ - u16 pause_time = I40E_DEFAULT_PAUSE_TIME; - u16 refresh_time = pause_time/2; - u8 first_pfc_prio = 0; - u32 link_speed = 0; - u8 num_pfc_tc = 0; - u8 tc2pfc = 0; - u32 reg = 0; - u8 i; - - /* Get Number of PFC TCs and TC2PFC map */ - for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) { - if (pfc_en & (1 << i)) { - if (!first_pfc_prio) - first_pfc_prio = i; - /* Set bit for the PFC TC */ - tc2pfc |= 1 << prio_tc[i]; - num_pfc_tc++; - } - } - - link_speed = hw->phy.link_info.link_speed; - switch (link_speed) { - case I40E_LINK_SPEED_10GB: - reg = rd32(hw, I40E_PRTDCB_MFLCN); - reg |= (1 << I40E_PRTDCB_MFLCN_DPF_SHIFT) & - I40E_PRTDCB_MFLCN_DPF_MASK; - reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK; - reg &= ~I40E_PRTDCB_MFLCN_RPFCE_MASK; - if (pfc_en) { - reg |= (1 << I40E_PRTDCB_MFLCN_RPFCM_SHIFT) & - I40E_PRTDCB_MFLCN_RPFCM_MASK; - reg |= ((u32)pfc_en << I40E_PRTDCB_MFLCN_RPFCE_SHIFT) & - I40E_PRTDCB_MFLCN_RPFCE_MASK; - } - wr32(hw, I40E_PRTDCB_MFLCN, reg); - - reg = rd32(hw, I40E_PRTDCB_FCCFG); - reg &= ~I40E_PRTDCB_FCCFG_TFCE_MASK; - if (pfc_en) - reg |= (2 << I40E_PRTDCB_FCCFG_TFCE_SHIFT) & - I40E_PRTDCB_FCCFG_TFCE_MASK; - wr32(hw, I40E_PRTDCB_FCCFG, reg); - - /* FCTTV and FCRTV to be set by default */ - break; - case I40E_LINK_SPEED_40GB: - reg = rd32(hw, I40E_PRTMAC_HSEC_CTL_RX_ENABLE_GPP); - reg &= ~I40E_PRTMAC_HSEC_CTL_RX_ENABLE_GPP_HSEC_CTL_RX_ENABLE_GPP_MASK; - wr32(hw, I40E_PRTMAC_HSEC_CTL_RX_ENABLE_GPP, reg); - - reg = rd32(hw, I40E_PRTMAC_HSEC_CTL_RX_ENABLE_PPP); - reg &= ~I40E_PRTMAC_HSEC_CTL_RX_ENABLE_GPP_HSEC_CTL_RX_ENABLE_GPP_MASK; - reg |= (1 << - I40E_PRTMAC_HSEC_CTL_RX_ENABLE_PPP_HSEC_CTL_RX_ENABLE_PPP_SHIFT) & - I40E_PRTMAC_HSEC_CTL_RX_ENABLE_PPP_HSEC_CTL_RX_ENABLE_PPP_MASK; - wr32(hw, I40E_PRTMAC_HSEC_CTL_RX_ENABLE_PPP, reg); - - reg = rd32(hw, I40E_PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE); - reg &= ~I40E_PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE_HSEC_CTL_RX_PAUSE_ENABLE_MASK; - reg |= ((u32)pfc_en << - I40E_PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE_HSEC_CTL_RX_PAUSE_ENABLE_SHIFT) & - I40E_PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE_HSEC_CTL_RX_PAUSE_ENABLE_MASK; - wr32(hw, I40E_PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE, reg); - - reg = rd32(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_ENABLE); - reg &= ~I40E_PRTMAC_HSEC_CTL_TX_PAUSE_ENABLE_HSEC_CTL_TX_PAUSE_ENABLE_MASK; - reg |= ((u32)pfc_en << - I40E_PRTMAC_HSEC_CTL_TX_PAUSE_ENABLE_HSEC_CTL_TX_PAUSE_ENABLE_SHIFT) & - I40E_PRTMAC_HSEC_CTL_TX_PAUSE_ENABLE_HSEC_CTL_TX_PAUSE_ENABLE_MASK; - wr32(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_ENABLE, reg); - - for (i = 0; i < I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_MAX_INDEX; i++) { - reg = rd32(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(i)); - reg &= ~I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_MASK; - if (pfc_en) { - reg |= ((u32)refresh_time << - I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_SHIFT) & - I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_MASK; - } - wr32(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(i), reg); - } - /* - * PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA default value is 0xFFFF - * for all user priorities - */ - break; - } - - reg = rd32(hw, I40E_PRTDCB_TC2PFC); - reg &= ~I40E_PRTDCB_TC2PFC_TC2PFC_MASK; - reg |= ((u32)tc2pfc << I40E_PRTDCB_TC2PFC_TC2PFC_SHIFT) & - I40E_PRTDCB_TC2PFC_TC2PFC_MASK; - wr32(hw, I40E_PRTDCB_TC2PFC, reg); - - reg = rd32(hw, I40E_PRTDCB_RUP); - reg &= ~I40E_PRTDCB_RUP_NOVLANUP_MASK; - reg |= ((u32)first_pfc_prio << I40E_PRTDCB_RUP_NOVLANUP_SHIFT) & - I40E_PRTDCB_RUP_NOVLANUP_MASK; - wr32(hw, I40E_PRTDCB_RUP, reg); - - reg = rd32(hw, I40E_PRTDCB_TDPMC); - reg &= ~I40E_PRTDCB_TDPMC_TCPM_MODE_MASK; - if (num_pfc_tc > 2) { - reg |= (1 << I40E_PRTDCB_TDPMC_TCPM_MODE_SHIFT) & - I40E_PRTDCB_TDPMC_TCPM_MODE_MASK; - } - wr32(hw, I40E_PRTDCB_TDPMC, reg); - - reg = rd32(hw, I40E_PRTDCB_TCPMC); - reg &= ~I40E_PRTDCB_TCPMC_TCPM_MODE_MASK; - if (num_pfc_tc > 2) { - reg |= (1 << I40E_PRTDCB_TCPMC_TCPM_MODE_SHIFT) & - I40E_PRTDCB_TCPMC_TCPM_MODE_MASK; - } - wr32(hw, I40E_PRTDCB_TCPMC, reg); -} - -/** - * i40e_dcb_hw_set_num_tc - * @hw: pointer to the hw struct - * @num_tc: number of traffic classes - * - * Configure number of traffic classes in HW - **/ -void i40e_dcb_hw_set_num_tc(struct i40e_hw *hw, u8 num_tc) -{ - u32 reg = rd32(hw, I40E_PRTDCB_GENC); - - reg &= ~I40E_PRTDCB_GENC_NUMTC_MASK; - reg |= ((u32)num_tc << I40E_PRTDCB_GENC_NUMTC_SHIFT) & - I40E_PRTDCB_GENC_NUMTC_MASK; - wr32(hw, I40E_PRTDCB_GENC, reg); -} - -/** - * i40e_dcb_hw_get_num_tc - * @hw: pointer to the hw struct - * - * Returns number of traffic classes configured in HW - **/ -u8 i40e_dcb_hw_get_num_tc(struct i40e_hw *hw) -{ - u32 reg = rd32(hw, I40E_PRTDCB_GENC); - - return (reg >> I40E_PRTDCB_GENC_NUMTC_SHIFT) & - I40E_PRTDCB_GENC_NUMTC_MASK; -} - -/** - * i40e_dcb_hw_rx_ets_bw_config - * @hw: pointer to the hw struct - * @bw_share: Bandwidth share indexed per traffic class - * @mode: Strict Priority or Round Robin mode between UP sharing same - * traffic class - * @prio_type: TC is ETS enabled or strict priority - * - * Configure HW Rx ETS bandwidth as part of DCB configuration. - **/ -void i40e_dcb_hw_rx_ets_bw_config(struct i40e_hw *hw, u8 *bw_share, - u8 *mode, u8 *prio_type) -{ - u32 reg = 0; - u8 i = 0; - - for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) { - reg = rd32(hw, I40E_PRTDCB_RETSTCC(i)); - reg &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK | - I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK | - I40E_PRTDCB_RETSTCC_ETSTC_SHIFT); - reg |= ((u32)bw_share[i] << I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) & - I40E_PRTDCB_RETSTCC_BWSHARE_MASK; - reg |= ((u32)mode[i] << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) & - I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK; - reg |= ((u32)prio_type[i] << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) & - I40E_PRTDCB_RETSTCC_ETSTC_MASK; - wr32(hw, I40E_PRTDCB_RETSTCC(i), reg); - } -} - -/** - * i40e_dcb_hw_rx_ets_bw_config - * @hw: pointer to the hw struct - * @prio_tc: priority to tc assignment indexed by priority - * - * Configure HW Rx UP2TC map as part of DCB configuration. - **/ -void i40e_dcb_hw_rx_up2tc_config(struct i40e_hw *hw, u8 *prio_tc) -{ - u32 reg = 0; - -#define I40E_UP2TC_REG(val, i) \ - ((val << I40E_PRTDCB_RUP2TC_UP##i##TC_SHIFT) & \ - I40E_PRTDCB_RUP2TC_UP##i##TC_MASK) - - reg = rd32(hw, I40E_PRTDCB_RUP2TC); - reg |= I40E_UP2TC_REG(prio_tc[0], 0); - reg |= I40E_UP2TC_REG(prio_tc[1], 1); - reg |= I40E_UP2TC_REG(prio_tc[2], 2); - reg |= I40E_UP2TC_REG(prio_tc[3], 3); - reg |= I40E_UP2TC_REG(prio_tc[4], 4); - reg |= I40E_UP2TC_REG(prio_tc[5], 5); - reg |= I40E_UP2TC_REG(prio_tc[6], 6); - reg |= I40E_UP2TC_REG(prio_tc[7], 7); - wr32(hw, I40E_PRTDCB_RUP2TC, reg); -} - -/** - * i40e_dcb_hw_calculate_pool_sizes - * @hw: pointer to the hw struct - * @num_ports: Number of available ports on the device - * @eee_enabled: EEE enabled for the given port - * @pfc_en: Bit map of PFC enabled traffic classes - * @mfs_tc: Array of max frame size for each traffic class - * - * Calculate the shared and dedicated per TC pool sizes, - * watermarks and threshold values. - **/ -void i40e_dcb_hw_calculate_pool_sizes(struct i40e_hw *hw, - u8 num_ports, bool eee_enabled, - u8 pfc_en, u32 *mfs_tc, - struct i40e_rx_pb_config *pb_cfg) -{ - u32 pool_size[I40E_MAX_TRAFFIC_CLASS]; - u32 high_wm[I40E_MAX_TRAFFIC_CLASS]; - u32 low_wm[I40E_MAX_TRAFFIC_CLASS]; - int shared_pool_size = 0; /* Need signed variable */ - u32 total_pool_size = 0; - u32 port_pb_size = 0; - u32 mfs_max = 0; - u32 pcirtt = 0; - u8 i = 0; - - /* Get the MFS(max) for the port */ - for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) { - if (mfs_tc[i] > mfs_max) - mfs_max = mfs_tc[i]; - } - - pcirtt = I40E_BT2B(I40E_PCIRTT_LINK_SPEED_10G); - - /* Calculate effective Rx PB size per port */ - port_pb_size = (I40E_DEVICE_RPB_SIZE/num_ports); - if (eee_enabled) - port_pb_size -= I40E_BT2B(I40E_EEE_TX_LPI_EXIT_TIME); - port_pb_size -= mfs_max; - - /* Step 1 Calculating tc pool/shared pool sizes and watermarks */ - for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) { - if (pfc_en & (1 << i)) { - low_wm[i] = (2 * mfs_tc[i]) + pcirtt; - high_wm[i] = low_wm[i]; - high_wm[i] += ((mfs_max > I40E_MAX_FRAME_SIZE) - ? mfs_max : I40E_MAX_FRAME_SIZE); - pool_size[i] = high_wm[i]; - pool_size[i] += I40E_BT2B(I40E_STD_DV_TC(mfs_max, - mfs_tc[i])); - } else { - low_wm[i] = 0; - pool_size[i] = (2 * mfs_tc[i]) + pcirtt; - high_wm[i] = pool_size[i]; - } - total_pool_size += pool_size[i]; - } - - shared_pool_size = port_pb_size - total_pool_size; - if (shared_pool_size > 0) { - pb_cfg->shared_pool_size = shared_pool_size; - pb_cfg->shared_pool_high_wm = shared_pool_size; - pb_cfg->shared_pool_low_wm = 0; - for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) { - pb_cfg->shared_pool_low_thresh[i] = 0; - pb_cfg->shared_pool_high_thresh[i] = shared_pool_size; - pb_cfg->tc_pool_size[i] = pool_size[i]; - pb_cfg->tc_pool_high_wm[i] = high_wm[i]; - pb_cfg->tc_pool_low_wm[i] = low_wm[i]; - } - - } else { - i40e_debug(hw, I40E_DEBUG_DCB, - "The shared pool size for the port is negative %d.\n", - shared_pool_size); - } -} - -/** - * i40e_dcb_hw_rx_pb_config - * @hw: pointer to the hw struct - * @old_pb_cfg: Existing Rx Packet buffer configuration - * @new_pb_cfg: New Rx Packet buffer configuration - * - * Program the Rx Packet Buffer registers. - **/ -void i40e_dcb_hw_rx_pb_config(struct i40e_hw *hw, - struct i40e_rx_pb_config *old_pb_cfg, - struct i40e_rx_pb_config *new_pb_cfg) -{ - u32 old_val = 0; - u32 new_val = 0; - u32 reg = 0; - u8 i = 0; - - /* Program the shared pool low water mark per port if decreasing */ - old_val = old_pb_cfg->shared_pool_low_wm; - new_val = new_pb_cfg->shared_pool_low_wm; - if (new_val < old_val) { - reg = rd32(hw, I40E_PRTRPB_SLW); - reg &= ~I40E_PRTRPB_SLW_SLW_MASK; - reg |= (new_val << I40E_PRTRPB_SLW_SLW_SHIFT) & - I40E_PRTRPB_SLW_SLW_MASK; - wr32(hw, I40E_PRTRPB_SLW, reg); - } - - /* Program the shared pool low threshold and tc pool - * low water mark per TC that are decreasing. - */ - for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) { - old_val = old_pb_cfg->shared_pool_low_thresh[i]; - new_val = new_pb_cfg->shared_pool_low_thresh[i]; - if (new_val < old_val) { - reg = rd32(hw, I40E_PRTRPB_SLT(i)); - reg &= ~I40E_PRTRPB_SLT_SLT_TCN_MASK; - reg |= (new_val << I40E_PRTRPB_SLT_SLT_TCN_SHIFT) & - I40E_PRTRPB_SLT_SLT_TCN_MASK; - wr32(hw, I40E_PRTRPB_SLT(i), reg); - } - - old_val = old_pb_cfg->tc_pool_low_wm[i]; - new_val = new_pb_cfg->tc_pool_low_wm[i]; - if (new_val < old_val) { - reg = rd32(hw, I40E_PRTRPB_DLW(i)); - reg &= ~I40E_PRTRPB_DLW_DLW_TCN_MASK; - reg |= (new_val << I40E_PRTRPB_DLW_DLW_TCN_SHIFT) & - I40E_PRTRPB_DLW_DLW_TCN_MASK; - wr32(hw, I40E_PRTRPB_DLW(i), reg); - } - } - - /* Program the shared pool high water mark per port if decreasing */ - old_val = old_pb_cfg->shared_pool_high_wm; - new_val = new_pb_cfg->shared_pool_high_wm; - if (new_val < old_val) { - reg = rd32(hw, I40E_PRTRPB_SHW); - reg &= ~I40E_PRTRPB_SHW_SHW_MASK; - reg |= (new_val << I40E_PRTRPB_SHW_SHW_SHIFT) & - I40E_PRTRPB_SHW_SHW_MASK; - wr32(hw, I40E_PRTRPB_SHW, reg); - } - - /* Program the shared pool high threshold and tc pool - * high water mark per TC that are decreasing. - */ - for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) { - old_val = old_pb_cfg->shared_pool_high_thresh[i]; - new_val = new_pb_cfg->shared_pool_high_thresh[i]; - if (new_val < old_val) { - reg = rd32(hw, I40E_PRTRPB_SHT(i)); - reg &= ~I40E_PRTRPB_SHT_SHT_TCN_MASK; - reg |= (new_val << I40E_PRTRPB_SHT_SHT_TCN_SHIFT) & - I40E_PRTRPB_SHT_SHT_TCN_MASK; - wr32(hw, I40E_PRTRPB_SHT(i), reg); - } - - old_val = old_pb_cfg->tc_pool_high_wm[i]; - new_val = new_pb_cfg->tc_pool_high_wm[i]; - if (new_val < old_val) { - reg = rd32(hw, I40E_PRTRPB_DHW(i)); - reg &= ~I40E_PRTRPB_DHW_DHW_TCN_MASK; - reg |= (new_val << I40E_PRTRPB_DHW_DHW_TCN_SHIFT) & - I40E_PRTRPB_DHW_DHW_TCN_MASK; - wr32(hw, I40E_PRTRPB_DHW(i), reg); - } - } - - /* Write Dedicated Pool Sizes per TC */ - for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) { - new_val = new_pb_cfg->tc_pool_size[i]; - reg = rd32(hw, I40E_PRTRPB_DPS(i)); - reg &= ~I40E_PRTRPB_DPS_DPS_TCN_MASK; - reg |= (new_val << I40E_PRTRPB_DPS_DPS_TCN_SHIFT) & - I40E_PRTRPB_DPS_DPS_TCN_MASK; - wr32(hw, I40E_PRTRPB_DPS(i), reg); - } - - /* Write Shared Pool Size per port */ - new_val = new_pb_cfg->shared_pool_size; - reg = rd32(hw, I40E_PRTRPB_SPS); - reg &= ~I40E_PRTRPB_SPS_SPS_MASK; - reg |= (new_val << I40E_PRTRPB_SPS_SPS_SHIFT) & - I40E_PRTRPB_SPS_SPS_MASK; - wr32(hw, I40E_PRTRPB_SPS, reg); - - /* Program the shared pool low water mark per port if increasing */ - old_val = old_pb_cfg->shared_pool_low_wm; - new_val = new_pb_cfg->shared_pool_low_wm; - if (new_val > old_val) { - reg = rd32(hw, I40E_PRTRPB_SLW); - reg &= ~I40E_PRTRPB_SLW_SLW_MASK; - reg |= (new_val << I40E_PRTRPB_SLW_SLW_SHIFT) & - I40E_PRTRPB_SLW_SLW_MASK; - wr32(hw, I40E_PRTRPB_SLW, reg); - } - - /* Program the shared pool low threshold and tc pool - * low water mark per TC that are increasing. - */ - for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) { - old_val = old_pb_cfg->shared_pool_low_thresh[i]; - new_val = new_pb_cfg->shared_pool_low_thresh[i]; - if (new_val > old_val) { - reg = rd32(hw, I40E_PRTRPB_SLT(i)); - reg &= ~I40E_PRTRPB_SLT_SLT_TCN_MASK; - reg |= (new_val << I40E_PRTRPB_SLT_SLT_TCN_SHIFT) & - I40E_PRTRPB_SLT_SLT_TCN_MASK; - wr32(hw, I40E_PRTRPB_SLT(i), reg); - } - - old_val = old_pb_cfg->tc_pool_low_wm[i]; - new_val = new_pb_cfg->tc_pool_low_wm[i]; - if (new_val > old_val) { - reg = rd32(hw, I40E_PRTRPB_DLW(i)); - reg &= ~I40E_PRTRPB_DLW_DLW_TCN_MASK; - reg |= (new_val << I40E_PRTRPB_DLW_DLW_TCN_SHIFT) & - I40E_PRTRPB_DLW_DLW_TCN_MASK; - wr32(hw, I40E_PRTRPB_DLW(i), reg); - } - } - - /* Program the shared pool high water mark per port if increasing */ - old_val = old_pb_cfg->shared_pool_high_wm; - new_val = new_pb_cfg->shared_pool_high_wm; - if (new_val > old_val) { - reg = rd32(hw, I40E_PRTRPB_SHW); - reg &= ~I40E_PRTRPB_SHW_SHW_MASK; - reg |= (new_val << I40E_PRTRPB_SHW_SHW_SHIFT) & - I40E_PRTRPB_SHW_SHW_MASK; - wr32(hw, I40E_PRTRPB_SHW, reg); - } - - /* Program the shared pool high threshold and tc pool - * high water mark per TC that are increasing. - */ - for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) { - old_val = old_pb_cfg->shared_pool_high_thresh[i]; - new_val = new_pb_cfg->shared_pool_high_thresh[i]; - if (new_val > old_val) { - reg = rd32(hw, I40E_PRTRPB_SHT(i)); - reg &= ~I40E_PRTRPB_SHT_SHT_TCN_MASK; - reg |= (new_val << I40E_PRTRPB_SHT_SHT_TCN_SHIFT) & - I40E_PRTRPB_SHT_SHT_TCN_MASK; - wr32(hw, I40E_PRTRPB_SHT(i), reg); - } - - old_val = old_pb_cfg->tc_pool_high_wm[i]; - new_val = new_pb_cfg->tc_pool_high_wm[i]; - if (new_val > old_val) { - reg = rd32(hw, I40E_PRTRPB_DHW(i)); - reg &= ~I40E_PRTRPB_DHW_DHW_TCN_MASK; - reg |= (new_val << I40E_PRTRPB_DHW_DHW_TCN_SHIFT) & - I40E_PRTRPB_DHW_DHW_TCN_MASK; - wr32(hw, I40E_PRTRPB_DHW(i), reg); - } - } -} - -/** - * i40e_read_lldp_cfg - read LLDP Configuration data from NVM - * @hw: pointer to the HW structure - * @lldp_cfg: pointer to hold lldp configuration variables - * - * Reads the LLDP configuration data from NVM - **/ -enum i40e_status_code i40e_read_lldp_cfg(struct i40e_hw *hw, - struct i40e_lldp_variables *lldp_cfg) -{ - enum i40e_status_code ret = I40E_SUCCESS; - struct i40e_emp_settings_module emp_ptr; - u32 offset = 0; - - if (!lldp_cfg) - return I40E_ERR_PARAM; - - ret = i40e_acquire_nvm(hw, I40E_RESOURCE_READ); - if (ret != I40E_SUCCESS) - goto err_lldp_cfg; - - ret = i40e_aq_read_nvm(hw, I40E_SR_EMP_MODULE_PTR, 0, - sizeof(emp_ptr), (u8 *)&emp_ptr, - true, NULL); - i40e_release_nvm(hw); - if (ret != I40E_SUCCESS) - goto err_lldp_cfg; - - /* Calculate the byte offset for LLDP config pointer */ - offset = (2 * emp_ptr.lldp_cfg_ptr); - offset += (2 * I40E_NVM_LLDP_CFG_PTR); - ret = i40e_acquire_nvm(hw, I40E_RESOURCE_READ); - if (ret != I40E_SUCCESS) - goto err_lldp_cfg; - - ret = i40e_aq_read_nvm(hw, I40E_SR_EMP_MODULE_PTR, offset, - sizeof(struct i40e_lldp_variables), - (u8 *)lldp_cfg, - true, NULL); - i40e_release_nvm(hw); - -err_lldp_cfg: - return ret; -} -#endif /* I40E_DCB_SW */ diff --git a/lib/librte_pmd_i40e/i40e/i40e_dcb.h b/lib/librte_pmd_i40e/i40e/i40e_dcb.h index 77f1d49..2261e08 100644 --- a/lib/librte_pmd_i40e/i40e/i40e_dcb.h +++ b/lib/librte_pmd_i40e/i40e/i40e_dcb.h @@ -149,109 +149,6 @@ struct i40e_dcbx_variables { u32 deftsaassignment; }; -#ifdef I40E_DCB_SW -/* Data structures to pass for SW DCBX */ -struct i40e_rx_pb_config { - u32 shared_pool_size; - u32 shared_pool_high_wm; - u32 shared_pool_low_wm; - u32 shared_pool_high_thresh[I40E_MAX_TRAFFIC_CLASS]; - u32 shared_pool_low_thresh[I40E_MAX_TRAFFIC_CLASS]; - u32 tc_pool_size[I40E_MAX_TRAFFIC_CLASS]; - u32 tc_pool_high_wm[I40E_MAX_TRAFFIC_CLASS]; - u32 tc_pool_low_wm[I40E_MAX_TRAFFIC_CLASS]; -}; - -enum i40e_dcb_arbiter_mode { - I40E_DCB_ARB_MODE_STRICT_PRIORITY = 0, - I40E_DCB_ARB_MODE_ROUND_ROBIN = 1 -}; - -#define I40E_DEFAULT_PAUSE_TIME 0xffff -#define I40E_MAX_FRAME_SIZE 4608 /* 4.5 KB */ - -#define I40E_DEVICE_RPB_SIZE 968000 /* 968 KB */ - -/* BitTimes (BT) conversion */ -#define I40E_BT2KB(BT) ((BT + (8 * 1024 - 1)) / (8 * 1024)) -#define I40E_B2BT(BT) (BT * 8) -#define I40E_BT2B(BT) ((BT + (8 - 1)) / (8)) - -/* Max Frame(TC) = MFS(max) + MFS(TC) */ -#define I40E_MAX_FRAME_TC(mfs_max, mfs_tc) I40E_B2BT(mfs_max + mfs_tc) - -/* EEE Tx LPI Exit time in Bit Times */ -#define I40E_EEE_TX_LPI_EXIT_TIME 142500 - -/* PCI Round Trip Time in Bit Times */ -#define I40E_PCIRTT_LINK_SPEED_10G 20000 -#define I40E_PCIRTT_BYTE_LINK_SPEED_20G 40000 -#define I40E_PCIRTT_BYTE_LINK_SPEED_40G 80000 - -/* PFC Frame Delay Bit Times */ -#define I40E_PFC_FRAME_DELAY 672 - -/* Worst case Cable (10GBase-T) Delay Bit Times */ -#define I40E_CABLE_DELAY 5556 - -/* Higher Layer Delay @10G Bit Times */ -#define I40E_HIGHER_LAYER_DELAY_10G 6144 - -/* Interface Delays in Bit Times */ -/* TODO: Add for other link speeds 20G/40G/etc. */ -#define I40E_INTERFACE_DELAY_10G_MAC_CONTROL 8192 -#define I40E_INTERFACE_DELAY_10G_MAC 8192 -#define I40E_INTERFACE_DELAY_10G_RS 8192 - -#define I40E_INTERFACE_DELAY_XGXS 2048 -#define I40E_INTERFACE_DELAY_XAUI 2048 - -#define I40E_INTERFACE_DELAY_10G_BASEX_PCS 2048 -#define I40E_INTERFACE_DELAY_10G_BASER_PCS 3584 -#define I40E_INTERFACE_DELAY_LX4_PMD 512 -#define I40E_INTERFACE_DELAY_CX4_PMD 512 -#define I40E_INTERFACE_DELAY_SERIAL_PMA 512 -#define I40E_INTERFACE_DELAY_PMD 512 - -#define I40E_INTERFACE_DELAY_10G_BASET 25600 - -/* delay values for with 10G BaseT in Bit Times */ -#define I40E_INTERFACE_DELAY_10G_COPPER \ - (I40E_INTERFACE_DELAY_10G_MAC + (2 * I40E_INTERFACE_DELAY_XAUI) \ - + I40E_INTERFACE_DELAY_10G_BASET) -#define I40E_DV_TC(mfs_max, mfs_tc) \ - ((2 * I40E_MAX_FRAME_TC(mfs_max, mfs_tc)) \ - + I40E_PFC_FRAME_DELAY \ - + (2 * I40E_CABLE_DELAY) \ - + (2 * I40E_INTERFACE_DELAY_10G_COPPER) \ - + I40E_HIGHER_LAYER_DELAY_10G) -#define I40E_STD_DV_TC(mfs_max, mfs_tc) \ - (I40E_DV_TC(mfs_max, mfs_tc) + I40E_B2BT(mfs_max)) - -enum i40e_status_code i40e_process_lldp_event(struct i40e_hw *hw, - struct i40e_arq_event_info *e); -/* APIs for SW DCBX */ -void i40e_dcb_hw_rx_fifo_config(struct i40e_hw *hw, - enum i40e_dcb_arbiter_mode ets_mode, - enum i40e_dcb_arbiter_mode non_ets_mode, - u32 max_exponent, u8 lltc_map); -void i40e_dcb_hw_rx_cmd_monitor_config(struct i40e_hw *hw, - u8 num_tc, u8 num_ports); -void i40e_dcb_hw_pfc_config(struct i40e_hw *hw, - u8 pfc_en, u8 *prio_tc); -void i40e_dcb_hw_set_num_tc(struct i40e_hw *hw, u8 num_tc); -u8 i40e_dcb_hw_get_num_tc(struct i40e_hw *hw); -void i40e_dcb_hw_rx_ets_bw_config(struct i40e_hw *hw, u8 *bw_share, - u8 *mode, u8 *prio_type); -void i40e_dcb_hw_rx_up2tc_config(struct i40e_hw *hw, u8 *prio_tc); -void i40e_dcb_hw_calculate_pool_sizes(struct i40e_hw *hw, - u8 num_ports, bool eee_enabled, - u8 pfc_en, u32 *mfs_tc, - struct i40e_rx_pb_config *pb_cfg); -void i40e_dcb_hw_rx_pb_config(struct i40e_hw *hw, - struct i40e_rx_pb_config *old_pb_cfg, - struct i40e_rx_pb_config *new_pb_cfg); -#endif /* I40E_DCB_SW */ enum i40e_status_code i40e_get_dcbx_status(struct i40e_hw *hw, u16 *status); enum i40e_status_code i40e_lldp_to_dcb_config(u8 *lldpmib, diff --git a/lib/librte_pmd_i40e/i40e/i40e_prototype.h b/lib/librte_pmd_i40e/i40e/i40e_prototype.h index cac5963..e559569 100644 --- a/lib/librte_pmd_i40e/i40e/i40e_prototype.h +++ b/lib/librte_pmd_i40e/i40e/i40e_prototype.h @@ -323,12 +323,6 @@ enum i40e_status_code i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw, struct i40e_asq_cmd_details *cmd_details); enum i40e_status_code i40e_aq_resume_port_tx(struct i40e_hw *hw, struct i40e_asq_cmd_details *cmd_details); -#ifdef I40E_DCB_SW -enum i40e_status_code i40e_aq_suspend_port_tx(struct i40e_hw *hw, u16 seid, - struct i40e_asq_cmd_details *cmd_details); -enum i40e_status_code i40e_read_lldp_cfg(struct i40e_hw *hw, - struct i40e_lldp_variables *lldp_cfg); -#endif /* I40E_DCB_SW */ enum i40e_status_code i40e_aq_add_cloud_filters(struct i40e_hw *hw, u16 vsi, struct i40e_aqc_add_remove_cloud_filters_element_data *filters, diff --git a/lib/librte_pmd_i40e/i40e/i40e_type.h b/lib/librte_pmd_i40e/i40e/i40e_type.h index aca8102..004967a 100644 --- a/lib/librte_pmd_i40e/i40e/i40e_type.h +++ b/lib/librte_pmd_i40e/i40e/i40e_type.h @@ -1403,46 +1403,6 @@ enum i40e_reset_type { I40E_RESET_GLOBR = 2, I40E_RESET_EMPR = 3, }; -#ifdef I40E_DCB_SW - -/* EMP Settings Module Header Section */ -struct i40e_emp_settings_module { - u16 length; - u16 fw_params; - u16 reserved; - u16 features; - u16 oem_cfg; - u16 pfalloc_ptr; - u16 eee_variables; - u16 phy_cap_lan0_ptr; - u16 phy_cap_lan1_ptr; - u16 phy_cap_lan2_ptr; - u16 phy_cap_lan3_ptr; - u16 phy_map_lan0_ptr; - u16 phy_map_lan1_ptr; - u16 phy_map_lan2_ptr; - u16 phy_map_lan3_ptr; - u16 lldp_cfg_ptr; - u16 ltr_max_snoop; - u16 ltr_max_no_snoop; - u16 ltr_delta; - u16 ltr_grade_value; - u16 lldp_tlv_ptr; - u16 crc8; -}; - -/* IEEE 802.1AB LLDP Agent Variables from NVM */ -#define I40E_NVM_LLDP_CFG_PTR 0xF -struct i40e_lldp_variables { - u16 length; - u16 adminstatus; - u16 msgfasttx; - u16 msgtxinterval; - u16 txparams; - u16 timers; - u16 crc8; -}; -#endif /* I40E_DCB_SW */ /* Offsets into Alternate Ram */ #define I40E_ALT_STRUCT_FIRST_PF_OFFSET 0 /* in dwords */