[v3,00/24] Support LoongArch architecture

  Dear team,
The following patch set is intended to support DPDK running on LoongArch
architecture.

LoongArch is the general processor architecture of Loongson and is a new
RISC ISA, which is a bit like MIPS or RISC-V.

The online documents of LoongArch are here:
	https://loongson.github.io/LoongArch-Documentation/README-EN.html

The latest cross compile tool chain can be downloaded from:
	https://github.com/loongson/build-tools

v3:
    - add URL for cross compile tool chain
	- remove rte_lpm_lsx.h which was a dummy vector implementation
      because there is already a scalar implementation, thanks to
      Michal Mazurek
    - modify the name of compiler for cross compiling
    - remove useless variable in meson.build

v2:
    - use standard atomics of toolchain to implement
      atomic operations
    - implement spinlock based on standard atomics    

Min Zhou (24):
  eal/loongarch: add atomic operations for LoongArch
  eal/loongarch: add byte order operations for LoongArch
  eal/loongarch: add cpu cycle operations for LoongArch
  eal/loongarch: add prefetch operations for LoongArch
  eal/loongarch: add spinlock operations for LoongArch
  eal/loongarch: add cpu flag checks for LoongArch
  eal/loongarch: add dummy vector memcpy for LoongArch
  eal/loongarch: add io operations for LoongArch
  eal/loongarch: add mcslock operations for LoongArch
  eal/loongarch: add pause operations for LoongArch
  eal/loongarch: add pflock operations for LoongArch
  eal/loongarch: add rwlock operations for LoongArch
  eal/loongarch: add ticketlock operations for LoongArch
  eal/loongarch: add power operations for LoongArch
  eal/loongarch: add hypervisor operations for LoongArch
  mem: add huge page size definition for LoongArch
  eal/linux: set eal base address for LoongArch
  meson: introduce LoongArch architecture
  test/xmmt_ops: add dummy vector implementation for LoongArch
  ixgbe: add dummy vector implementation for LoongArch
  i40e: add dummy vector implementation for LoongArch
  tap: add system call number for LoongArch
  memif: add system call number for LoongArch
  maintainers: claim responsibility for LoongArch

 MAINTAINERS                                   |   9 +
 app/test/test_xmmt_ops.h                      |  17 ++
 .../loongarch/loongarch_loongarch64_linux_gcc |  16 ++
 config/loongarch/meson.build                  |  43 +++
 drivers/net/i40e/i40e_rxtx_vec_lsx.c          |  54 ++++
 drivers/net/i40e/meson.build                  |   2 +
 drivers/net/ixgbe/ixgbe_rxtx_vec_lsx.c        |  60 +++++
 drivers/net/ixgbe/meson.build                 |   2 +
 drivers/net/memif/rte_eth_memif.h             |   2 +-
 drivers/net/tap/tap_bpf.h                     |   2 +-
 lib/eal/include/rte_memory.h                  |   1 +
 lib/eal/include/rte_memzone.h                 |   1 +
 lib/eal/linux/eal_memory.c                    |   4 +
 lib/eal/loongarch/include/meson.build         |  21 ++
 lib/eal/loongarch/include/rte_atomic.h        | 253 ++++++++++++++++++
 lib/eal/loongarch/include/rte_byteorder.h     |  46 ++++
 lib/eal/loongarch/include/rte_cpuflags.h      |  39 +++
 lib/eal/loongarch/include/rte_cycles.h        |  53 ++++
 lib/eal/loongarch/include/rte_io.h            |  18 ++
 lib/eal/loongarch/include/rte_mcslock.h       |  18 ++
 lib/eal/loongarch/include/rte_memcpy.h        | 193 +++++++++++++
 lib/eal/loongarch/include/rte_pause.h         |  24 ++
 lib/eal/loongarch/include/rte_pflock.h        |  17 ++
 .../loongarch/include/rte_power_intrinsics.h  |  20 ++
 lib/eal/loongarch/include/rte_prefetch.h      |  47 ++++
 lib/eal/loongarch/include/rte_rwlock.h        |  42 +++
 lib/eal/loongarch/include/rte_spinlock.h      |  90 +++++++
 lib/eal/loongarch/include/rte_ticketlock.h    |  18 ++
 lib/eal/loongarch/include/rte_vect.h          |  46 ++++
 lib/eal/loongarch/meson.build                 |  11 +
 lib/eal/loongarch/rte_cpuflags.c              |  94 +++++++
 lib/eal/loongarch/rte_cycles.c                |  45 ++++
 lib/eal/loongarch/rte_hypervisor.c            |  11 +
 lib/eal/loongarch/rte_power_intrinsics.c      |  51 ++++
 meson.build                                   |   2 +
 35 files changed, 1370 insertions(+), 2 deletions(-)
 create mode 100644 config/loongarch/loongarch_loongarch64_linux_gcc
 create mode 100644 config/loongarch/meson.build
 create mode 100644 drivers/net/i40e/i40e_rxtx_vec_lsx.c
 create mode 100644 drivers/net/ixgbe/ixgbe_rxtx_vec_lsx.c
 create mode 100644 lib/eal/loongarch/include/meson.build
 create mode 100644 lib/eal/loongarch/include/rte_atomic.h
 create mode 100644 lib/eal/loongarch/include/rte_byteorder.h
 create mode 100644 lib/eal/loongarch/include/rte_cpuflags.h
 create mode 100644 lib/eal/loongarch/include/rte_cycles.h
 create mode 100644 lib/eal/loongarch/include/rte_io.h
 create mode 100644 lib/eal/loongarch/include/rte_mcslock.h
 create mode 100644 lib/eal/loongarch/include/rte_memcpy.h
 create mode 100644 lib/eal/loongarch/include/rte_pause.h
 create mode 100644 lib/eal/loongarch/include/rte_pflock.h
 create mode 100644 lib/eal/loongarch/include/rte_power_intrinsics.h
 create mode 100644 lib/eal/loongarch/include/rte_prefetch.h
 create mode 100644 lib/eal/loongarch/include/rte_rwlock.h
 create mode 100644 lib/eal/loongarch/include/rte_spinlock.h
 create mode 100644 lib/eal/loongarch/include/rte_ticketlock.h
 create mode 100644 lib/eal/loongarch/include/rte_vect.h
 create mode 100644 lib/eal/loongarch/meson.build
 create mode 100644 lib/eal/loongarch/rte_cpuflags.c
 create mode 100644 lib/eal/loongarch/rte_cycles.c
 create mode 100644 lib/eal/loongarch/rte_hypervisor.c
 create mode 100644 lib/eal/loongarch/rte_power_intrinsics.c
  

Hello,

On Mon, Jun 6, 2022 at 3:11 PM Min Zhou <zhoumin@loongson.cn> wrote:
>
> Dear team,
> The following patch set is intended to support DPDK running on LoongArch
> architecture.
>
> LoongArch is the general processor architecture of Loongson and is a new
> RISC ISA, which is a bit like MIPS or RISC-V.
>
> The online documents of LoongArch are here:
>         https://loongson.github.io/LoongArch-Documentation/README-EN.html
>
> The latest cross compile tool chain can be downloaded from:
>         https://github.com/loongson/build-tools
>
> v3:
>     - add URL for cross compile tool chain
>         - remove rte_lpm_lsx.h which was a dummy vector implementation
>       because there is already a scalar implementation, thanks to
>       Michal Mazurek
>     - modify the name of compiler for cross compiling
>     - remove useless variable in meson.build
>
> v2:
>     - use standard atomics of toolchain to implement
>       atomic operations
>     - implement spinlock based on standard atomics

Thanks for porting DPDK to a new architecture.

I am unsure of what this architecture status is wrt to the upstream
Linux kernel and wrt to main distributions support.
Could you give some details?

Otherwise, I did not look at the series yet, but it needs to be
rebased on the main repository, there have been quite some changes
since this original submission.
How will this architecture be integrated wrt CI: GHA? sending your hw
to UNH lab? or maybe do you have plans for your own CI servers?
  

On 2022年07月21日 00:33, David Marchand wrote:
> Hello,
>
> On Mon, Jun 6, 2022 at 3:11 PM Min Zhou <zhoumin@loongson.cn> wrote:
>> Dear team,
>> The following patch set is intended to support DPDK running on LoongArch
>> architecture.
>>
>> LoongArch is the general processor architecture of Loongson and is a new
>> RISC ISA, which is a bit like MIPS or RISC-V.
>>
>> The online documents of LoongArch are here:
>>          https://loongson.github.io/LoongArch-Documentation/README-EN.html
>>
>> The latest cross compile tool chain can be downloaded from:
>>          https://github.com/loongson/build-tools
>>
>> v3:
>>      - add URL for cross compile tool chain
>>          - remove rte_lpm_lsx.h which was a dummy vector implementation
>>        because there is already a scalar implementation, thanks to
>>        Michal Mazurek
>>      - modify the name of compiler for cross compiling
>>      - remove useless variable in meson.build
>>
>> v2:
>>      - use standard atomics of toolchain to implement
>>        atomic operations
>>      - implement spinlock based on standard atomics
> Thanks for porting DPDK to a new architecture.
>
> I am unsure of what this architecture status is wrt to the upstream
> Linux kernel and wrt to main distributions support.
> Could you give some details?
The upstream Linux kernel has merged the majority of the LoongArch
architecture code for Linux 5.19, including the final system call interface
and all core functionality. However, It still misses some patches to add
support for other subsystems, which currently under review. Due to
some of the code not yet passing review, Linux 5.19 cannot boot on
LoongArch system. Presumably by the time of the Linux 5.20 kernel
cycle later this summer the rest of the required driver support will
pass review to yield a bootable LoongArch system.

The GLIBC LoongArch support is likely to be mainlined for GLIBC 2.36
on or around August 1st, 2022.

The LoongArch port for GCC has been merged for GCC 12.

For lacking the complete upstream support for these significant projects,
there is no main distribution yet for upstream Linux kernel of LoongArch.
>
> Otherwise, I did not look at the series yet, but it needs to be
> rebased on the main repository, there have been quite some changes
> since this original submission.
I have rebased the patchset on the main repository and will send it later.
> How will this architecture be integrated wrt CI: GHA? sending your hw
> to UNH lab? or maybe do you have plans for your own CI servers?
There are some public repositories that all have loongson branches
maintained by ourselves, which will be submit to upstream project,
under Loongson organization on github: https://github.com/loongson.
We can build a CI server that can be accessed externally based on
these repositories. However, I want to know how to integrate the
CI server we build into the patch review process of DPDK.
>
--
Thanks,
Min Zhou