From patchwork Thu Feb 13 12:38:48 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gavin Hu X-Patchwork-Id: 65787 Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 2A352A0542; Thu, 13 Feb 2020 13:43:50 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 7901C1BFB5; Thu, 13 Feb 2020 13:43:49 +0100 (CET) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by dpdk.org (Postfix) with ESMTP id B8EB61BFB4 for ; Thu, 13 Feb 2020 13:43:48 +0100 (CET) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 3B7411FB; Thu, 13 Feb 2020 04:43:48 -0800 (PST) Received: from net-arm-thunderx2-04.shanghai.arm.com (net-arm-thunderx2-04.shanghai.arm.com [10.169.40.184]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 02F4D3F6CF; Thu, 13 Feb 2020 04:43:41 -0800 (PST) From: Gavin Hu To: dev@dpdk.org Cc: nd@arm.com, david.marchand@redhat.com, thomas@monjalon.net, rasland@mellanox.com, drc@linux.vnet.ibm.com, bruce.richardson@intel.com, konstantin.ananyev@intel.com, matan@mellanox.com, shahafs@mellanox.com, viacheslavo@mellanox.com, jerinj@marvell.com, Honnappa.Nagarahalli@arm.com, ruifeng.wang@arm.com, phil.yang@arm.com, joyce.kong@arm.com, steve.capper@arm.com Date: Thu, 13 Feb 2020 20:38:48 +0800 Message-Id: <20200213123854.203566-1-gavin.hu@arm.com> X-Mailer: git-send-email 2.17.1 Subject: [dpdk-dev] [PATCH RFC v1 0/6] barrier fix and optimization for mlx5 on aarch64 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Using just sufficient barriers really matters to performance. Insufficient barriers will cause issues while barriers stronger than required, especially in the fast path is a performance killer. In the joint preliminary testing between Arm and Ampere, 8%~13% performance was measured. Gavin Hu (5): net/mlx5: relax the barrier for UAR write net/mlx5: use cio barrier before the BF WQE net/mlx5: add missing barrier net/mlx5: add descriptive comment for a barrier net/mlx5: non-cacheable mapping defaulted for aarch64 Phil Yang (1): net/mlx5: relaxed ordering for multi-packet RQ buffer refcnt drivers/net/mlx5/mlx5_rxq.c | 5 +++-- drivers/net/mlx5/mlx5_rxtx.c | 16 +++++++++------- drivers/net/mlx5/mlx5_rxtx.h | 11 ++++++++--- drivers/net/mlx5/mlx5_txq.c | 4 ++++ 4 files changed, 24 insertions(+), 12 deletions(-)