@@ -18,3 +18,4 @@ implementer_id = '0x56'
part_number = '0xd08'
max_lcores = 16
max_numa_nodes = 1
+disabled_drivers = ['bus/dpaa', 'bus/fslmc', 'common/dpaax']
@@ -2,6 +2,9 @@
# Copyright(c) 2017 Intel Corporation.
# Copyright(c) 2017 Cavium, Inc
+# disable Arm drivers for all builds
+disabled_drivers += ['net/avp', 'net/fm10k']
+
# common flags to all aarch64 builds, with lowest priority
flags_common = [
# Accelerate rte_memcpy. Be sure to run unit test (memcpy_perf_autotest)
@@ -16,9 +19,6 @@ flags_common = [
# ['RTE_ARM64_MEMCPY_ALIGN_MASK', 0xF],
# ['RTE_ARM64_MEMCPY_STRICT_ALIGN', false],
- ['RTE_NET_FM10K', false],
- ['RTE_NET_AVP', false],
-
['RTE_SCHED_VECTOR', false],
['RTE_ARM_USE_WFE', false],
['RTE_ARCH_ARM64', true],
@@ -126,7 +126,6 @@ implementer_cavium = {
['RTE_MACHINE', '"octeontx2"'],
['RTE_ARM_FEATURE_ATOMICS', true],
['RTE_USE_C11_MEM_MODEL', true],
- ['RTE_EAL_IGB_UIO', false],
['RTE_MAX_LCORE', 36],
['RTE_MAX_NUMA_NODES', 1]
]
@@ -143,3 +143,7 @@ There are other options you may specify in a cross file to tailor the build::
Supported extra configuration
max_numa_nodes = n # will set RTE_MAX_NUMA_NODES
max_lcores = n # will set RTE_MAX_LCORE
+
+ disabled_drivers = ['bus/dpaa', 'crypto'] # add disabled drivers
+ # valid values are directories (optionally with their subdirs)
+ # in the drivers directory
@@ -18,9 +18,13 @@ subdirs = [
'baseband', # depends on common and bus.
]
-disabled_drivers = run_command(list_dir_globs, get_option('disable_drivers'),
+disabled_drivers += run_command(list_dir_globs, get_option('disable_drivers'),
).stdout().split()
+if meson.is_cross_build()
+ disabled_drivers += meson.get_cross_property('disabled_drivers', [])
+endif
+
default_cflags = machine_args
default_cflags += ['-DALLOW_EXPERIMENTAL_API']
default_cflags += ['-DALLOW_INTERNAL_API']
@@ -21,6 +21,7 @@ dpdk_drivers = []
dpdk_extra_ldflags = []
dpdk_libs_disabled = []
dpdk_drvs_disabled = []
+disabled_drivers = []
abi_version_file = files('ABI_VERSION')
if host_machine.cpu_family().startswith('x86')