diff mbox series

net/mlx5: fix validate MPLSoGRE with GRE key

Message ID 767ac1c511fcb95715b1498e187789a7ffe7871d.1605009114.git.jackmin@nvidia.com (mailing list archive)
State Accepted, archived
Delegated to: Raslan Darawsheh
Headers
Series net/mlx5: fix validate MPLSoGRE with GRE key |

Checks

Context Check Description
ci/checkpatch success coding style OK
ci/iol-broadcom-Functional success Functional Testing PASS
ci/iol-broadcom-Performance success Performance Testing PASS
ci/iol-testing success Testing PASS
ci/iol-intel-Performance success Performance Testing PASS
ci/iol-mellanox-Performance success Performance Testing PASS
ci/travis-robot success Travis build: passed
ci/Intel-compilation success Compilation OK
ci/iol-intel-Functional success Functional Testing PASS

Commit Message

Xiaoyu Min Nov. 10, 2020, 11:59 a.m. UTC 
  From: Xiaoyu Min <jackmin@nvidia.com>

Currently PMD only accept flow which item_mpls directly follow item_gre,
means to match the GRE header without GRE optional field key in MPLSoGRE
encapsulation.

However, for the MPLSoGRE, the GRE header could have the optional field
(i.e, key) according to the RFC. So PMD need to accept this.

Add MLX5_FLOW_LAYER_GRE_KEY into allowed prev_layer to fix

Fixes: a7a0365565a4 ("net/mlx5: match GRE key and present bits")
Cc: stable@dpdk.org

Signed-off-by: Xiaoyu Min <jackmin@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
---
 drivers/net/mlx5/mlx5_flow.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

Comments

Thomas Monjalon Nov. 13, 2020, 7:07 p.m. UTC | #1 
10/11/2020 12:59, Xiaoyu Min:
> From: Xiaoyu Min <jackmin@nvidia.com>
> 
> Currently PMD only accept flow which item_mpls directly follow item_gre,
> means to match the GRE header without GRE optional field key in MPLSoGRE
> encapsulation.
> 
> However, for the MPLSoGRE, the GRE header could have the optional field
> (i.e, key) according to the RFC. So PMD need to accept this.
> 
> Add MLX5_FLOW_LAYER_GRE_KEY into allowed prev_layer to fix
> 
> Fixes: a7a0365565a4 ("net/mlx5: match GRE key and present bits")
> Cc: stable@dpdk.org
> 
> Signed-off-by: Xiaoyu Min <jackmin@nvidia.com>
> Acked-by: Matan Azrad <matan@nvidia.com>

Applied in next-net-mlx, thanks.
diff mbox series

Patch

diff --git a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c
index 92adfcacca..50d2bbb617 100644
--- a/drivers/net/mlx5/mlx5_flow.c
+++ b/drivers/net/mlx5/mlx5_flow.c
@@ -2746,7 +2746,8 @@  mlx5_flow_validate_item_mpls(struct rte_eth_dev *dev __rte_unused,
 	/* MPLS over IP, UDP, GRE is allowed */
 	if (!(prev_layer & (MLX5_FLOW_LAYER_OUTER_L3 |
 			    MLX5_FLOW_LAYER_OUTER_L4_UDP |
-			    MLX5_FLOW_LAYER_GRE)))
+			    MLX5_FLOW_LAYER_GRE |
+			    MLX5_FLOW_LAYER_GRE_KEY)))
 		return rte_flow_error_set(error, EINVAL,
 					  RTE_FLOW_ERROR_TYPE_ITEM, item,
 					  "protocol filtering not compatible"