From patchwork Mon Oct 26 16:37:46 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bing Zhao X-Patchwork-Id: 82209 X-Patchwork-Delegate: rasland@nvidia.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 22686A04DD; Mon, 26 Oct 2020 17:40:20 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id B95763257; Mon, 26 Oct 2020 17:38:43 +0100 (CET) Received: from git-send-mailer.rdmz.labs.mlnx (unknown [37.142.13.130]) by dpdk.org (Postfix) with ESMTP id 100322C2E for ; Mon, 26 Oct 2020 17:38:41 +0100 (CET) From: Bing Zhao To: viacheslavo@mellanox.com, matan@mellanox.com Cc: dev@dpdk.org, orika@nvidia.com, rasland@nvidia.com Date: Tue, 27 Oct 2020 00:37:46 +0800 Message-Id: <1603730267-267228-7-git-send-email-bingz@nvidia.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1603730267-267228-1-git-send-email-bingz@nvidia.com> References: <1602166620-46303-1-git-send-email-bingz@nvidia.com> <1603730267-267228-1-git-send-email-bingz@nvidia.com> Subject: [dpdk-dev] [PATCH v3 6/7] net/mlx5: not split hairpin flow in explicit mode X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" In the current implementation, the hairpin flow will be split into two flows implicitly if there is some action that only belongs to the Tx part. A Tx device flow will be inserted by the mlx5 PMD itself. In hairpin between two ports, the explicit Tx flow mode will be the only one to be supported. It is not the appropriate behavior to insert a Tx flow into another device implicitly. The application could create any flow as it likes and has full control of the user flows. Hairpin flows will have no difference from standard flows and the application can decide how to chain Rx and Tx flows together. Even in the single port hairpin, this explicit Tx flow mode could also be supported. When checking if the hairpin needs to be split, it will just return if the hairpin queue is with "tx_explicit" attribute. Then in the following steps for validation and translation, the code path will be the same as that for standard flows. Signed-off-by: Bing Zhao Acked-by: Viacheslav Ovsiienko --- v3: remove unnecessary checking of hairpin queue type --- drivers/net/mlx5/mlx5_flow.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c index 949b9ce..4756cf9 100644 --- a/drivers/net/mlx5/mlx5_flow.c +++ b/drivers/net/mlx5/mlx5_flow.c @@ -3618,6 +3618,7 @@ struct rte_flow_shared_action * const struct rte_flow_action_queue *queue; const struct rte_flow_action_rss *rss; const struct rte_flow_action_raw_encap *raw_encap; + const struct rte_eth_hairpin_conf *conf; if (!attr->ingress) return 0; @@ -3627,8 +3628,8 @@ struct rte_flow_shared_action * queue = actions->conf; if (queue == NULL) return 0; - if (mlx5_rxq_get_type(dev, queue->index) != - MLX5_RXQ_TYPE_HAIRPIN) + conf = mlx5_rxq_get_hairpin_conf(dev, queue->index); + if (conf != NULL && !!conf->tx_explicit) return 0; queue_action = 1; action_n++; @@ -3637,8 +3638,8 @@ struct rte_flow_shared_action * rss = actions->conf; if (rss == NULL || rss->queue_num == 0) return 0; - if (mlx5_rxq_get_type(dev, rss->queue[0]) != - MLX5_RXQ_TYPE_HAIRPIN) + conf = mlx5_rxq_get_hairpin_conf(dev, rss->queue[0]); + if (conf != NULL && !!conf->tx_explicit) return 0; queue_action = 1; action_n++;