[v2,6/6] net/mlx5: not split hairpin flow in explicit mode
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Commit Message
In the current implementation, the hairpin flow will be split into
two flows implicitly if there is some action that only belongs to the
TX part. A TX device flow will be inserted by the mlx5 PMD itself.
In hairpin between two ports, the explicit TX flow mode will be the
only one to be supported. It is not the appropriate behavior to
insert a TX flow into another device implicitly. The application
could create any flow as it likes and has full control of the user
flows. Hairpin flows will have no difference from standard flows and
the application can decide how to chain RX and TX flows together.
Even in the single port hairpin, this explicit TX flow mode could
also be supported.
When checking if the hairpin needs to be split, just return if the
hairpin queue is with "tx_explicit" attribute. Then in the following
steps for validation and translation, the code path will be the same
as that for standard flows.
Signed-off-by: Bing Zhao <bingz@nvidia.com>
---
drivers/net/mlx5/mlx5_flow.c | 7 +++++++
1 file changed, 7 insertions(+)
Comments
> -----Original Message-----
> From: Bing Zhao <bingz@nvidia.com>
> Sent: Thursday, October 22, 2020 17:07
> To: viacheslavo@mellanox.com; matan@mellanox.com
> Cc: dev@dpdk.org; Ori Kam <orika@nvidia.com>; Raslan Darawsheh
> <rasland@nvidia.com>
> Subject: [PATCH v2 6/6] net/mlx5: not split hairpin flow in explicit mode
>
> In the current implementation, the hairpin flow will be split into two flows
> implicitly if there is some action that only belongs to the TX part. A TX device
> flow will be inserted by the mlx5 PMD itself.
>
> In hairpin between two ports, the explicit TX flow mode will be the only one to
> be supported. It is not the appropriate behavior to insert a TX flow into
> another device implicitly. The application could create any flow as it likes and
> has full control of the user flows. Hairpin flows will have no difference from
> standard flows and the application can decide how to chain RX and TX flows
> together.
>
> Even in the single port hairpin, this explicit TX flow mode could also be
> supported.
>
> When checking if the hairpin needs to be split, just return if the hairpin queue
> is with "tx_explicit" attribute. Then in the following steps for validation and
> translation, the code path will be the same as that for standard flows.
>
> Signed-off-by: Bing Zhao <bingz@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
> ---
> drivers/net/mlx5/mlx5_flow.c | 7 +++++++
> 1 file changed, 7 insertions(+)
>
@@ -3261,6 +3261,7 @@ struct mlx5_flow_tunnel_info {
const struct rte_flow_action_queue *queue;
const struct rte_flow_action_rss *rss;
const struct rte_flow_action_raw_encap *raw_encap;
+ const struct rte_eth_hairpin_conf *conf;
if (!attr->ingress)
return 0;
@@ -3273,6 +3274,9 @@ struct mlx5_flow_tunnel_info {
if (mlx5_rxq_get_type(dev, queue->index) !=
MLX5_RXQ_TYPE_HAIRPIN)
return 0;
+ conf = mlx5_rxq_get_hairpin_conf(dev, queue->index);
+ if (!!conf->tx_explicit)
+ return 0;
queue_action = 1;
action_n++;
break;
@@ -3283,6 +3287,9 @@ struct mlx5_flow_tunnel_info {
if (mlx5_rxq_get_type(dev, rss->queue[0]) !=
MLX5_RXQ_TYPE_HAIRPIN)
return 0;
+ conf = mlx5_rxq_get_hairpin_conf(dev, rss->queue[0]);
+ if (conf != NULL && !!conf->tx_explicit)
+ return 0;
queue_action = 1;
action_n++;
break;