From patchwork Thu Oct 22 12:24:07 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Rybchenko X-Patchwork-Id: 81788 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id DF74CA04DD; Thu, 22 Oct 2020 14:25:10 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 9403AA9E7; Thu, 22 Oct 2020 14:24:41 +0200 (CEST) Received: from dispatch1-us1.ppe-hosted.com (dispatch1-us1.ppe-hosted.com [148.163.129.52]) by dpdk.org (Postfix) with ESMTP id 4FB31A9C9 for ; Thu, 22 Oct 2020 14:24:35 +0200 (CEST) Received: from mx1-us1.ppe-hosted.com (unknown [10.7.65.64]) by dispatch1-us1.ppe-hosted.com (PPE Hosted ESMTP Server) with ESMTP id C553F60053 for ; Thu, 22 Oct 2020 12:24:33 +0000 (UTC) Received: from us4-mdac16-71.ut7.mdlocal (unknown [10.7.64.190]) by mx1-us1.ppe-hosted.com (PPE Hosted ESMTP Server) with ESMTP id C4EE62009B for ; Thu, 22 Oct 2020 12:24:33 +0000 (UTC) X-Virus-Scanned: Proofpoint Essentials engine Received: from mx1-us1.ppe-hosted.com (unknown [10.7.65.174]) by mx1-us1.ppe-hosted.com (PPE Hosted ESMTP Server) with ESMTPS id 4D8DC220059 for ; Thu, 22 Oct 2020 12:24:33 +0000 (UTC) Received: from webmail.solarflare.com (uk.solarflare.com [193.34.186.16]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-SHA384 (256/256 bits)) (No client certificate requested) by mx1-us1.ppe-hosted.com (PPE Hosted ESMTP Server) with ESMTPS id 0315B1C006C for ; Thu, 22 Oct 2020 12:24:33 +0000 (UTC) Received: from ukex01.SolarFlarecom.com (10.17.10.4) by ukex01.SolarFlarecom.com (10.17.10.4) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 22 Oct 2020 13:24:28 +0100 Received: from opal.uk.solarflarecom.com (10.17.10.1) by ukex01.SolarFlarecom.com (10.17.10.4) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 22 Oct 2020 13:24:28 +0100 Received: from ukv-loginhost.uk.solarflarecom.com (ukv-loginhost.uk.solarflarecom.com [10.17.10.39]) by opal.uk.solarflarecom.com (8.13.8/8.13.8) with ESMTP id 09MCOSc8029644 for ; Thu, 22 Oct 2020 13:24:28 +0100 Received: from ukv-loginhost.uk.solarflarecom.com (localhost [127.0.0.1]) by ukv-loginhost.uk.solarflarecom.com (Postfix) with ESMTP id 96DA01613BE for ; Thu, 22 Oct 2020 13:24:28 +0100 (BST) From: Andrew Rybchenko To: Date: Thu, 22 Oct 2020 13:24:07 +0100 Message-ID: <1603369447-28388-3-git-send-email-arybchenko@solarflare.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1603369447-28388-1-git-send-email-arybchenko@solarflare.com> References: <1603369447-28388-1-git-send-email-arybchenko@solarflare.com> MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-12.5.0.1300-8.6.1012-25740.003 X-TM-AS-Result: No-0.919500-8.000000-10 X-TMASE-MatchedRID: NPDRjTX9xLiqfSQfLa/SNxvkdCFTAtdJCyj2gR0nEXU9phCcpYL3wciT Wug2C4DNNNN0dk/lb45w5T4Iaj538mJZXQNDzktSKrDHzH6zmUXDIePmAHuyD7w2tvOM+/Mn7Vk pVDE/imLX463G6fDzeJOqbAAm8P7Iua4uqbY3uLVbUzvsaHW6BuRjZuXE0WlHHWtVZN0asThyUv NZqge9uG2HhQSQfQe0GMZ2/85B6XJArPgBK8zY0y0x8J2DopENUlUyzHUJOPf92ZWRCAbitMrU3 m4wf5VQ/l6vas/Ugqvv2WoTNgecbPcW+q+VX6KJggra2NOo2i2ZMySE2nqxBUp12IXZajx5RtUL 4XifTnv6OqajpqaZatTWDiU7V0XtlwV2iaAfSWcURSScn+QSXt0H8LFZNFG76sBnwpOylLOpk2b xy1ooXjb20zDNUPoFgmR+LLMzqI7PRf2ExiXxIPl2LD81bD7+nebvGMQrSQgX7+Slq420ybXW2c TdZbZ2nXFjB5w8iVQA5SS2XRjKFM+aZOIheolUvvUo0hZPhlzM/43UL1MJR37cGd19dSFd X-TM-AS-User-Approved-Sender: Yes X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--0.919500-8.000000 X-TMASE-Version: SMEX-12.5.0.1300-8.6.1012-25740.003 X-MDID: 1603369473-I8TdumJgs2fk X-PPE-DISP: 1603369473;I8TdumJgs2fk Subject: [dpdk-dev] [PATCH 3/3] net/sfc: support aarch64 architecture X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Enable the PMD build on aarch64. Signed-off-by: Andrew Rybchenko Reviewed-by: Andy Moreton --- config/arm/meson.build | 1 - doc/guides/nics/features/sfc_efx.ini | 1 + doc/guides/rel_notes/release_20_11.rst | 1 + drivers/common/sfc_efx/efsys.h | 17 +++++++++++++++++ drivers/common/sfc_efx/meson.build | 4 ++-- drivers/net/sfc/meson.build | 4 ++-- drivers/net/sfc/sfc_ef10.h | 9 +++++++++ 7 files changed, 32 insertions(+), 5 deletions(-) diff --git a/config/arm/meson.build b/config/arm/meson.build index b49203f..13f42cd 100644 --- a/config/arm/meson.build +++ b/config/arm/meson.build @@ -22,7 +22,6 @@ flags_common_default = [ # ['RTE_ARM64_MEMCPY_STRICT_ALIGN', false], ['RTE_NET_FM10K', false], - ['RTE_NET_SFC_EFX', false], ['RTE_NET_AVP', false], ['RTE_SCHED_VECTOR', false], diff --git a/doc/guides/nics/features/sfc_efx.ini b/doc/guides/nics/features/sfc_efx.ini index eca1427..213b6e1 100644 --- a/doc/guides/nics/features/sfc_efx.ini +++ b/doc/guides/nics/features/sfc_efx.ini @@ -40,4 +40,5 @@ Multiprocess aware = Y BSD nic_uio = Y Linux UIO = Y Linux VFIO = Y +ARMv8 = Y x86-64 = Y diff --git a/doc/guides/rel_notes/release_20_11.rst b/doc/guides/rel_notes/release_20_11.rst index fa666e0..fcf206a 100644 --- a/doc/guides/rel_notes/release_20_11.rst +++ b/doc/guides/rel_notes/release_20_11.rst @@ -167,6 +167,7 @@ New Features * Added SR-IOV PF support * Added Alveo SN1000 SmartNICs (EF100 architecture) support including flow API transfer rules for switch HW offload + * Added ARMv8 support * **Updated Virtio driver.** diff --git a/drivers/common/sfc_efx/efsys.h b/drivers/common/sfc_efx/efsys.h index 139f4d8..a3ae313 100644 --- a/drivers/common/sfc_efx/efsys.h +++ b/drivers/common/sfc_efx/efsys.h @@ -39,8 +39,25 @@ #define EFSYS_HAS_UINT64 1 #define EFSYS_USE_UINT64 1 +/* + * __SSE2__ is defined by a compiler if target architecture supports + * Streaming SIMD Extensions 2 (SSE2). __m128i is a data type used + * by the extension instructions. + */ +#if defined(__SSE2__) #define EFSYS_HAS_UINT128 1 typedef __m128i efsys_uint128_t; +/* + * __int128 and unsigned __int128 are compiler extensions (built-in types). + * __SIZEOF_INT128__ is defined by the compiler if these data types are + * available. + */ +#elif defined(__SIZEOF_INT128__) +#define EFSYS_HAS_UINT128 1 +typedef unsigned __int128 efsys_uint128_t; +#else +#error Unsigned 128-bit width integers support is required +#endif #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN #define EFSYS_IS_BIG_ENDIAN 1 diff --git a/drivers/common/sfc_efx/meson.build b/drivers/common/sfc_efx/meson.build index b7a0763..6cb9f07 100644 --- a/drivers/common/sfc_efx/meson.build +++ b/drivers/common/sfc_efx/meson.build @@ -5,9 +5,9 @@ # This software was jointly developed between OKTET Labs (under contract # for Solarflare) and Solarflare Communications, Inc. -if arch_subdir != 'x86' or not dpdk_conf.get('RTE_ARCH_64') +if (arch_subdir != 'x86' or not dpdk_conf.get('RTE_ARCH_64')) and (arch_subdir != 'arm' or not host_machine.cpu_family().startswith('aarch64')) build = false - reason = 'only supported on x86_64' + reason = 'only supported on x86_64 and aarch64' endif extra_flags = [] diff --git a/drivers/net/sfc/meson.build b/drivers/net/sfc/meson.build index 42b184c..be888bd 100644 --- a/drivers/net/sfc/meson.build +++ b/drivers/net/sfc/meson.build @@ -6,9 +6,9 @@ # This software was jointly developed between OKTET Labs (under contract # for Solarflare) and Solarflare Communications, Inc. -if arch_subdir != 'x86' or not dpdk_conf.get('RTE_ARCH_64') +if (arch_subdir != 'x86' or not dpdk_conf.get('RTE_ARCH_64')) and (arch_subdir != 'arm' or not host_machine.cpu_family().startswith('aarch64')) build = false - reason = 'only supported on x86_64' + reason = 'only supported on x86_64 and aarch64' endif extra_flags = [] diff --git a/drivers/net/sfc/sfc_ef10.h b/drivers/net/sfc/sfc_ef10.h index 7bca219..e13f43f 100644 --- a/drivers/net/sfc/sfc_ef10.h +++ b/drivers/net/sfc/sfc_ef10.h @@ -22,6 +22,15 @@ #define SFC_EF10_EV_QCLEAR_MASK (~(SFC_EF10_EV_PER_CACHE_LINE - 1)) +/* + * Use simple libefx-based implementation of the + * sfc_ef10_ev_qclear_cache_line() if SSE2 is not available + * since optimized implementation uses __m128i intrinsics. + */ +#ifndef __SSE2__ +#define SFC_EF10_EV_QCLEAR_USE_EFX +#endif + #if defined(SFC_EF10_EV_QCLEAR_USE_EFX) static inline void sfc_ef10_ev_qclear_cache_line(void *ptr)