diff mbox series

[v10,11/18] net/mlx5: check max SIMD bitwidth

Message ID 20201019134858.32507-12-david.marchand@redhat.com (mailing list archive)
State Accepted, archived
Delegated to: David Marchand
Headers
Series add max SIMD bitwidth to EAL |

Checks

Context Check Description
ci/checkpatch success coding style OK

Commit Message

David Marchand Oct. 19, 2020, 1:48 p.m. UTC 
  From: Ciara Power <ciara.power@intel.com>

When choosing a vector path to take, an extra condition must be
satisfied to ensure the max SIMD bitwidth allows for the CPU enabled
path.

Signed-off-by: Ciara Power <ciara.power@intel.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
---
v4: Updated enum name.
v2: Moved check for max bitwidth into existing check vec
    support function.
---
 drivers/net/mlx5/mlx5_rxtx_vec.c | 3 +++
 1 file changed, 3 insertions(+)
diff mbox series

Patch

diff --git a/drivers/net/mlx5/mlx5_rxtx_vec.c b/drivers/net/mlx5/mlx5_rxtx_vec.c
index 711dcd35fa..f083038682 100644
--- a/drivers/net/mlx5/mlx5_rxtx_vec.c
+++ b/drivers/net/mlx5/mlx5_rxtx_vec.c
@@ -10,6 +10,7 @@ 
 #include <rte_mbuf.h>
 #include <rte_mempool.h>
 #include <rte_prefetch.h>
+#include <rte_vect.h>
 
 #include <mlx5_glue.h>
 #include <mlx5_prm.h>
@@ -148,6 +149,8 @@  mlx5_check_vec_rx_support(struct rte_eth_dev *dev)
 	struct mlx5_priv *priv = dev->data->dev_private;
 	uint32_t i;
 
+	if (rte_vect_get_max_simd_bitwidth() < RTE_VECT_SIMD_128)
+		return -ENOTSUP;
 	if (!priv->config.rx_vec_en)
 		return -ENOTSUP;
 	if (mlx5_mprq_enabled(dev))