From patchwork Tue Oct 13 13:45:49 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Rybchenko X-Patchwork-Id: 80534 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id DD189A04B7; Tue, 13 Oct 2020 15:55:24 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id DD56B1DC3A; Tue, 13 Oct 2020 15:46:43 +0200 (CEST) Received: from dispatch1-us1.ppe-hosted.com (dispatch1-us1.ppe-hosted.com [67.231.154.164]) by dpdk.org (Postfix) with ESMTP id ACDB91DB8F for ; Tue, 13 Oct 2020 15:46:04 +0200 (CEST) Received: from mx1-us1.ppe-hosted.com (unknown [10.110.50.150]) by dispatch1-us1.ppe-hosted.com (PPE Hosted ESMTP Server) with ESMTP id 6256F20059 for ; Tue, 13 Oct 2020 13:46:04 +0000 (UTC) Received: from us4-mdac16-56.at1.mdlocal (unknown [10.110.48.199]) by mx1-us1.ppe-hosted.com (PPE Hosted ESMTP Server) with ESMTP id 5D4A1800A7 for ; Tue, 13 Oct 2020 13:46:04 +0000 (UTC) X-Virus-Scanned: Proofpoint Essentials engine Received: from mx1-us1.ppe-hosted.com (unknown [10.110.49.106]) by mx1-us1.ppe-hosted.com (PPE Hosted ESMTP Server) with ESMTPS id DFC3E100079 for ; Tue, 13 Oct 2020 13:46:03 +0000 (UTC) Received: from webmail.solarflare.com (uk.solarflare.com [193.34.186.16]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-SHA384 (256/256 bits)) (No client certificate requested) by mx1-us1.ppe-hosted.com (PPE Hosted ESMTP Server) with ESMTPS id A7C44B4005B for ; Tue, 13 Oct 2020 13:46:03 +0000 (UTC) Received: from ukex01.SolarFlarecom.com (10.17.10.4) by ukex01.SolarFlarecom.com (10.17.10.4) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 13 Oct 2020 14:45:57 +0100 Received: from opal.uk.solarflarecom.com (10.17.10.1) by ukex01.SolarFlarecom.com (10.17.10.4) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 13 Oct 2020 14:45:57 +0100 Received: from ukv-loginhost.uk.solarflarecom.com (ukv-loginhost.uk.solarflarecom.com [10.17.10.39]) by opal.uk.solarflarecom.com (8.13.8/8.13.8) with ESMTP id 09DDjvYV006146 for ; Tue, 13 Oct 2020 14:45:57 +0100 Received: from ukv-loginhost.uk.solarflarecom.com (localhost [127.0.0.1]) by ukv-loginhost.uk.solarflarecom.com (Postfix) with ESMTP id E7EB01613AB for ; Tue, 13 Oct 2020 14:45:56 +0100 (BST) From: Andrew Rybchenko To: Date: Tue, 13 Oct 2020 14:45:49 +0100 Message-ID: <1602596753-32282-33-git-send-email-arybchenko@solarflare.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1602596753-32282-1-git-send-email-arybchenko@solarflare.com> References: <1602596753-32282-1-git-send-email-arybchenko@solarflare.com> MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-12.5.0.1300-8.6.1012-25722.003 X-TM-AS-Result: No-5.979000-8.000000-10 X-TMASE-MatchedRID: rZWcR6FTFvk2jeY+Udg/IuFgDmzNVVKofo0lncdGFFPAJMh4mAwEG+Pd pDLFu49i8XVI39JCRnRM7g1j0AuHEWJZXQNDzktSh2VzUlo4HVN0ZH0LS0iojwVQtPavvwzP0iS XG6dWPltYTMLZxhDK/GzTTC+2Zzy2kLQe3uHqwd3J1E/nrJFED+imxgRHwEwm1l38M6aWfEgzdQ PozFjjwJUmJ/LD6bIVZ0xJsWXSiHCvvxILmKK/HBRFJJyf5BJe3QfwsVk0UbtuRXh7bFKB7pURK R/7eomdMbN3dta/FmUUNVKC1IbJWkW5VsT2TJUIlExlQIQeRG0= X-TM-AS-User-Approved-Sender: Yes X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--5.979000-8.000000 X-TMASE-Version: SMEX-12.5.0.1300-8.6.1012-25722.003 X-MDID: 1602596764-kmVwCKKqctoQ X-PPE-DISP: 1602596764;kmVwCKKqctoQ Subject: [dpdk-dev] [PATCH 32/36] net/sfc: support per-queue Rx RSS hash offload for EF100 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Riverhead allows to choose Rx prefix (which contains RSS hash value and valid flag) per queue. Signed-off-by: Andrew Rybchenko --- drivers/net/sfc/sfc_ef100_rx.c | 27 ++++++++++++++++++++++++--- 1 file changed, 24 insertions(+), 3 deletions(-) diff --git a/drivers/net/sfc/sfc_ef100_rx.c b/drivers/net/sfc/sfc_ef100_rx.c index 5d46d5bac1..6fb78b6e68 100644 --- a/drivers/net/sfc/sfc_ef100_rx.c +++ b/drivers/net/sfc/sfc_ef100_rx.c @@ -56,6 +56,7 @@ struct sfc_ef100_rxq { #define SFC_EF100_RXQ_STARTED 0x1 #define SFC_EF100_RXQ_NOT_RUNNING 0x2 #define SFC_EF100_RXQ_EXCEPTION 0x4 +#define SFC_EF100_RXQ_RSS_HASH 0x10 unsigned int ptr_mask; unsigned int evq_phase_bit_shift; unsigned int ready_pkts; @@ -349,14 +350,17 @@ static const efx_rx_prefix_layout_t sfc_ef100_rx_prefix_layout = { EFX_RX_PREFIX_FIELD(_name, ESF_GZ_RX_PREFIX_ ## _name, _big_endian) SFC_EF100_RX_PREFIX_FIELD(LENGTH, B_FALSE), + SFC_EF100_RX_PREFIX_FIELD(RSS_HASH_VALID, B_FALSE), SFC_EF100_RX_PREFIX_FIELD(CLASS, B_FALSE), + SFC_EF100_RX_PREFIX_FIELD(RSS_HASH, B_FALSE), #undef SFC_EF100_RX_PREFIX_FIELD } }; static bool -sfc_ef100_rx_prefix_to_offloads(const efx_oword_t *rx_prefix, +sfc_ef100_rx_prefix_to_offloads(const struct sfc_ef100_rxq *rxq, + const efx_oword_t *rx_prefix, struct rte_mbuf *m) { const efx_word_t *class; @@ -375,6 +379,15 @@ sfc_ef100_rx_prefix_to_offloads(const efx_oword_t *rx_prefix, m->packet_type = sfc_ef100_rx_class_decode(*class, &ol_flags); + if ((rxq->flags & SFC_EF100_RXQ_RSS_HASH) && + EFX_TEST_OWORD_BIT(rx_prefix[0], + ESF_GZ_RX_PREFIX_RSS_HASH_VALID_LBN)) { + ol_flags |= PKT_RX_RSS_HASH; + /* EFX_OWORD_FIELD converts little-endian to CPU */ + m->hash.rss = EFX_OWORD_FIELD(rx_prefix[0], + ESF_GZ_RX_PREFIX_RSS_HASH); + } + m->ol_flags = ol_flags; return true; } @@ -461,7 +474,7 @@ sfc_ef100_rx_process_ready_pkts(struct sfc_ef100_rxq *rxq, seg_len = RTE_MIN(pkt_len, rxq->buf_size - rxq->prefix_size); rte_pktmbuf_data_len(pkt) = seg_len; - deliver = sfc_ef100_rx_prefix_to_offloads(rx_prefix, pkt); + deliver = sfc_ef100_rx_prefix_to_offloads(rxq, rx_prefix, pkt); lastseg = pkt; while ((pkt_len -= seg_len) > 0) { @@ -740,6 +753,13 @@ sfc_ef100_rx_qstart(struct sfc_dp_rxq *dp_rxq, unsigned int evq_read_ptr, (1U << EFX_RX_PREFIX_FIELD_CLASS))) != 0) return ENOTSUP; + if ((unsup_rx_prefix_fields & + ((1U << EFX_RX_PREFIX_FIELD_RSS_HASH_VALID) | + (1U << EFX_RX_PREFIX_FIELD_RSS_HASH))) == 0) + rxq->flags |= SFC_EF100_RXQ_RSS_HASH; + else + rxq->flags &= ~SFC_EF100_RXQ_RSS_HASH; + rxq->prefix_size = pinfo->erpl_length; rxq->rearm_data = sfc_ef100_mk_mbuf_rearm_data(rxq->dp.dpq.port_id, rxq->prefix_size); @@ -812,7 +832,8 @@ struct sfc_dp_rx sfc_ef100_rx = { .queue_offload_capa = DEV_RX_OFFLOAD_CHECKSUM | DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | DEV_RX_OFFLOAD_OUTER_UDP_CKSUM | - DEV_RX_OFFLOAD_SCATTER, + DEV_RX_OFFLOAD_SCATTER | + DEV_RX_OFFLOAD_RSS_HASH, .get_dev_info = sfc_ef100_rx_get_dev_info, .qsize_up_rings = sfc_ef100_rx_qsize_up_rings, .qcreate = sfc_ef100_rx_qcreate,