From patchwork Tue Oct 13 13:45:50 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Rybchenko X-Patchwork-Id: 80525 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 6601BA04B7; Tue, 13 Oct 2020 15:52:02 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 053A01DC06; Tue, 13 Oct 2020 15:46:31 +0200 (CEST) Received: from dispatch1-us1.ppe-hosted.com (dispatch1-us1.ppe-hosted.com [67.231.154.164]) by dpdk.org (Postfix) with ESMTP id 2F8E61DB76 for ; Tue, 13 Oct 2020 15:46:05 +0200 (CEST) Received: from mx1-us1.ppe-hosted.com (unknown [10.110.50.143]) by dispatch1-us1.ppe-hosted.com (PPE Hosted ESMTP Server) with ESMTP id 852C820131 for ; Tue, 13 Oct 2020 13:46:04 +0000 (UTC) Received: from us4-mdac16-44.at1.mdlocal (unknown [10.110.48.15]) by mx1-us1.ppe-hosted.com (PPE Hosted ESMTP Server) with ESMTP id 83FE58009B for ; Tue, 13 Oct 2020 13:46:04 +0000 (UTC) X-Virus-Scanned: Proofpoint Essentials engine Received: from mx1-us1.ppe-hosted.com (unknown [10.110.50.7]) by mx1-us1.ppe-hosted.com (PPE Hosted ESMTP Server) with ESMTPS id 1934C40078 for ; Tue, 13 Oct 2020 13:46:04 +0000 (UTC) Received: from webmail.solarflare.com (uk.solarflare.com [193.34.186.16]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-SHA384 (256/256 bits)) (No client certificate requested) by mx1-us1.ppe-hosted.com (PPE Hosted ESMTP Server) with ESMTPS id D5A234C006B for ; Tue, 13 Oct 2020 13:46:03 +0000 (UTC) Received: from ukex01.SolarFlarecom.com (10.17.10.4) by ukex01.SolarFlarecom.com (10.17.10.4) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 13 Oct 2020 14:45:57 +0100 Received: from opal.uk.solarflarecom.com (10.17.10.1) by ukex01.SolarFlarecom.com (10.17.10.4) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 13 Oct 2020 14:45:57 +0100 Received: from ukv-loginhost.uk.solarflarecom.com (ukv-loginhost.uk.solarflarecom.com [10.17.10.39]) by opal.uk.solarflarecom.com (8.13.8/8.13.8) with ESMTP id 09DDjvT2006151 for ; Tue, 13 Oct 2020 14:45:57 +0100 Received: from ukv-loginhost.uk.solarflarecom.com (localhost [127.0.0.1]) by ukv-loginhost.uk.solarflarecom.com (Postfix) with ESMTP id 001171613A9 for ; Tue, 13 Oct 2020 14:45:56 +0100 (BST) From: Andrew Rybchenko To: Date: Tue, 13 Oct 2020 14:45:50 +0100 Message-ID: <1602596753-32282-34-git-send-email-arybchenko@solarflare.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1602596753-32282-1-git-send-email-arybchenko@solarflare.com> References: <1602596753-32282-1-git-send-email-arybchenko@solarflare.com> MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-12.5.0.1300-8.6.1012-25722.003 X-TM-AS-Result: No-3.462700-8.000000-10 X-TMASE-MatchedRID: n7nN31NWDDoxFOj6wQa550r0JusapgjyUg5zxCPHJW3iYlKox3ryNGdA jAKFDP1f8XVI39JCRnT/hOZJ+pyU4MxAixoJws1YA9lly13c/gF+jSWdx0YUUw6QlBHhBZuwQdb LhAjmhfnUBJDw8HKbPYtnJxTByjiPFfiIZsVUTbFlpwNsTvdlKSD8Ih+V5f0PmJBe2bRXwlOMBa f5zCPrtiZE5D95I7+IgDLqnrRlXrZ8nn9tnqel2MZW5ai5WKlydEJdfH7QpC/35b1HMLgKQJasO xqX3DMOs526WWxH2EmvrOzKj05N1tYxuvPDcqAqBBRIoi4MJLcT5h0f1A7wGaCWcDNU6cybT72c oBR9t306Iwx+LO2mj/hdZk++XZNksCh0GdVc0vmTRDpzG3k69Q== X-TM-AS-User-Approved-Sender: Yes X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--3.462700-8.000000 X-TMASE-Version: SMEX-12.5.0.1300-8.6.1012-25722.003 X-MDID: 1602596764-FlkeDD4RFhAi X-PPE-DISP: 1602596764;FlkeDD4RFhAi Subject: [dpdk-dev] [PATCH 33/36] net/sfc: support user mark and flag Rx for EF100 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Flow rules may be used mark packets. Support delivery of mark/flag values to user in mbuf fields. Signed-off-by: Andrew Rybchenko --- drivers/net/sfc/sfc_ef100_rx.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/drivers/net/sfc/sfc_ef100_rx.c b/drivers/net/sfc/sfc_ef100_rx.c index 6fb78b6e68..0623f6e574 100644 --- a/drivers/net/sfc/sfc_ef100_rx.c +++ b/drivers/net/sfc/sfc_ef100_rx.c @@ -57,6 +57,7 @@ struct sfc_ef100_rxq { #define SFC_EF100_RXQ_NOT_RUNNING 0x2 #define SFC_EF100_RXQ_EXCEPTION 0x4 #define SFC_EF100_RXQ_RSS_HASH 0x10 +#define SFC_EF100_RXQ_USER_MARK 0x20 unsigned int ptr_mask; unsigned int evq_phase_bit_shift; unsigned int ready_pkts; @@ -351,8 +352,10 @@ static const efx_rx_prefix_layout_t sfc_ef100_rx_prefix_layout = { SFC_EF100_RX_PREFIX_FIELD(LENGTH, B_FALSE), SFC_EF100_RX_PREFIX_FIELD(RSS_HASH_VALID, B_FALSE), + SFC_EF100_RX_PREFIX_FIELD(USER_FLAG, B_FALSE), SFC_EF100_RX_PREFIX_FIELD(CLASS, B_FALSE), SFC_EF100_RX_PREFIX_FIELD(RSS_HASH, B_FALSE), + SFC_EF100_RX_PREFIX_FIELD(USER_MARK, B_FALSE), #undef SFC_EF100_RX_PREFIX_FIELD } @@ -388,6 +391,14 @@ sfc_ef100_rx_prefix_to_offloads(const struct sfc_ef100_rxq *rxq, ESF_GZ_RX_PREFIX_RSS_HASH); } + if ((rxq->flags & SFC_EF100_RXQ_USER_MARK) && + EFX_TEST_OWORD_BIT(rx_prefix[0], ESF_GZ_RX_PREFIX_USER_FLAG_LBN)) { + ol_flags |= PKT_RX_FDIR_ID; + /* EFX_OWORD_FIELD converts little-endian to CPU */ + m->hash.fdir.hi = EFX_OWORD_FIELD(rx_prefix[0], + ESF_GZ_RX_PREFIX_USER_MARK); + } + m->ol_flags = ol_flags; return true; } @@ -760,6 +771,13 @@ sfc_ef100_rx_qstart(struct sfc_dp_rxq *dp_rxq, unsigned int evq_read_ptr, else rxq->flags &= ~SFC_EF100_RXQ_RSS_HASH; + if ((unsup_rx_prefix_fields & + ((1U << EFX_RX_PREFIX_FIELD_USER_FLAG) | + (1U << EFX_RX_PREFIX_FIELD_USER_MARK))) == 0) + rxq->flags |= SFC_EF100_RXQ_USER_MARK; + else + rxq->flags &= ~SFC_EF100_RXQ_USER_MARK; + rxq->prefix_size = pinfo->erpl_length; rxq->rearm_data = sfc_ef100_mk_mbuf_rearm_data(rxq->dp.dpq.port_id, rxq->prefix_size);