diff mbox series

[v5,09/17] net/ice: add checks for max SIMD bitwidth

Message ID	20201013110437.309110-10-ciara.power@intel.com (mailing list archive)
State	Superseded, archived
Delegated to:	David Marchand
Headers	IronPort-SDR: N7Kre/XJVz6QuOs/8lWngt+qwf5uRumPNJaDtNwJqg9LI2Ad0XsugvSMsuHVjVJ2ncC4nxgwed EFMHt9QuMMkg== IronPort-SDR: M3B+RdzBYoxWN0xSntnc797Tr9oKoX5W9OxW1BD0y7loQjNwtb0HT2LJ8OrhTI9o+q/4m+ZpgG mavK0B31w7+Q== From: Ciara Power <ciara.power@intel.com> To: dev@dpdk.org Cc: viktorin@rehivetech.com, ruifeng.wang@arm.com, jerinj@marvell.com, drc@linux.vnet.ibm.com, bruce.richardson@intel.com, konstantin.ananyev@intel.com, Ciara Power <ciara.power@intel.com>, Qiming Yang <qiming.yang@intel.com>, Qi Zhang <qi.z.zhang@intel.com> Date: Tue, 13 Oct 2020 12:04:29 +0100 Message-Id: <20201013110437.309110-10-ciara.power@intel.com> In-Reply-To: <20201013110437.309110-1-ciara.power@intel.com> References: <20200807155859.63888-1-ciara.power@intel.com> <20201013110437.309110-1-ciara.power@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Subject: [dpdk-dev] [PATCH v5 09/17] net/ice: add checks for max SIMD bitwidth Precedence: list Errors-To: dev-bounces@dpdk.org Sender: "dev" <dev-bounces@dpdk.org>
Series	add max SIMD bitwidth to EAL \| [v5,00/17] add max SIMD bitwidth to EAL [v5,01/17] eal: add max SIMD bitwidth [v5,02/17] doc: add detail on using max SIMD bitwidth [v5,03/17] net/i40e: add checks for max SIMD bitwidth [v5,04/17] net/axgbe: add checks for max SIMD bitwidth [v5,05/17] net/bnxt: add checks for max SIMD bitwidth [v5,06/17] net/enic: add checks for max SIMD bitwidth [v5,07/17] net/fm10k: add checks for max SIMD bitwidth [v5,08/17] net/iavf: add checks for max SIMD bitwidth [v5,09/17] net/ice: add checks for max SIMD bitwidth [v5,10/17] net/ixgbe: add checks for max SIMD bitwidth [v5,11/17] net/mlx5: add checks for max SIMD bitwidth [v5,12/17] net/virtio: add checks for max SIMD bitwidth [v5,13/17] distributor: add checks for max SIMD bitwidth [v5,14/17] member: add checks for max SIMD bitwidth [v5,15/17] efd: add checks for max SIMD bitwidth [v5,16/17] net: add checks for max SIMD bitwidth [v5,17/17] node: choose vector path at runtime

Checks

Context	Check	Description
ci/checkpatch	success	coding style OK

Commit Message

Ciara Power Oct. 13, 2020, 11:04 a.m. UTC

  When choosing a vector path to take, an extra condition must be
satisfied to ensure the max SIMD bitwidth allows for the CPU enabled
path.

Cc: Qiming Yang <qiming.yang@intel.com>
Cc: Qi Zhang <qi.z.zhang@intel.com>

Signed-off-by: Ciara Power <ciara.power@intel.com>

---
v4: Updated enum name.
---
 drivers/net/ice/ice_rxtx.c | 20 ++++++++++++++------
 1 file changed, 14 insertions(+), 6 deletions(-)

Comments

Qi Zhang Oct. 13, 2020, 12:11 p.m. UTC | #1

> -----Original Message-----
> From: Power, Ciara <ciara.power@intel.com>
> Sent: Tuesday, October 13, 2020 7:04 PM
> To: dev@dpdk.org
> Cc: viktorin@rehivetech.com; ruifeng.wang@arm.com; jerinj@marvell.com;
> drc@linux.vnet.ibm.com; Richardson, Bruce <bruce.richardson@intel.com>;
> Ananyev, Konstantin <konstantin.ananyev@intel.com>; Power, Ciara
> <ciara.power@intel.com>; Yang, Qiming <qiming.yang@intel.com>; Zhang, Qi
> Z <qi.z.zhang@intel.com>
> Subject: [PATCH v5 09/17] net/ice: add checks for max SIMD bitwidth
> 
> When choosing a vector path to take, an extra condition must be satisfied to
> ensure the max SIMD bitwidth allows for the CPU enabled path.
> 
> Cc: Qiming Yang <qiming.yang@intel.com>
> Cc: Qi Zhang <qi.z.zhang@intel.com>
> 
> Signed-off-by: Ciara Power <ciara.power@intel.com>

Acked-by: Qi Zhang <qi.z.zhang@intel.com>

diff mbox series

Patch

diff --git a/drivers/net/ice/ice_rxtx.c b/drivers/net/ice/ice_rxtx.c
index 93a0ac6918..0003ce2afe 100644
--- a/drivers/net/ice/ice_rxtx.c
+++ b/drivers/net/ice/ice_rxtx.c
@@ -2989,7 +2989,9 @@  ice_set_rx_function(struct rte_eth_dev *dev)
 	bool use_avx2 = false;
 
 	if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
-		if (!ice_rx_vec_dev_check(dev) && ad->rx_bulk_alloc_allowed) {
+		if (!ice_rx_vec_dev_check(dev) && ad->rx_bulk_alloc_allowed &&
+				rte_get_max_simd_bitwidth()
+				>= RTE_SIMD_128) {
 			ad->rx_vec_allowed = true;
 			for (i = 0; i < dev->data->nb_rx_queues; i++) {
 				rxq = dev->data->rx_queues[i];
@@ -2999,8 +3001,10 @@  ice_set_rx_function(struct rte_eth_dev *dev)
 				}
 			}
 
-			if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 ||
-			rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1)
+			if ((rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 ||
+			rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1) &&
+					rte_get_max_simd_bitwidth()
+					>= RTE_SIMD_256)
 				use_avx2 = true;
 
 		} else {
@@ -3167,7 +3171,9 @@  ice_set_tx_function(struct rte_eth_dev *dev)
 	bool use_avx2 = false;
 
 	if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
-		if (!ice_tx_vec_dev_check(dev)) {
+		if (!ice_tx_vec_dev_check(dev) &&
+				rte_get_max_simd_bitwidth()
+				>= RTE_SIMD_128) {
 			ad->tx_vec_allowed = true;
 			for (i = 0; i < dev->data->nb_tx_queues; i++) {
 				txq = dev->data->tx_queues[i];
@@ -3177,8 +3183,10 @@  ice_set_tx_function(struct rte_eth_dev *dev)
 				}
 			}
 
-			if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 ||
-			rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1)
+			if ((rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 ||
+			rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1) &&
+					rte_get_max_simd_bitwidth()
+					>= RTE_SIMD_256)
 				use_avx2 = true;
 
 		} else {